Abstract: The invention combines the repeater functions outlined in the IEEE 802.3 Standards, §27, and the 100BASE-TX PCS and PMA. The disclosed FEMR provides four ports in the PQFR packet of its 100 pins. Such extension ports allow multiple serial connections of the FEMR's, increasing the number of all ports on the repeaters. Therefore, the price of each repeater can be reduced to its minimum, and the serial device does not need an external logic circuit. Additionally, the serial device also supports the extension among built-in inter-repeaters used in stackable backplanes.

Abstract: The invention combines the repeater functions outlined in the IEEE 802.3 Standards, §27, and the 100BASE-TX PCS and PMA. The disclosed FEMR provides four ports in the PQFR packet of its 100 pins. Such extension ports allow multiple serial connections of the FEMR's, increasing the number of all ports on the repeaters. Therefore, the price of each repeater can be reduced to its minimum, and the serial device does not need an external logic circuit. Additionally, the serial device also supports the extension among built-in inter-repeaters used in stackable backplanes.

Abstract: A parallel signal processing device for high speed timing recovery in a high speed transfer network includes a plurality of data sampling processors (DSP), a central phase-error processor (CPP), and a recovered clock phase adjuster (RCPA. The sampling of transfer data, processing of sampling data, and adjustment of the recovered clock are executed by a plurality of data sampling processors for producing phase difference signals which are then transferred separately to a central phase-error processor. Phase-error adjustment signals for each data sampling processor are produced by the central phase-error processor, and the recovered clock phase for each data sampling processor is adjusted by the recovered clock phase adjuster according to the phase-error.

Abstract: A multiple rate waveshaping method and apparatus for converting transmission data into communications code synthesized waveforms having different protocol frequencies in the physical layer of the fast Ethernet utilizes two state machines which convert the transmission data into appropriate waveforms using predetermined wave shaping signals, the outputs of the state machines being multiplexed and transmitted over the Ethernet media using a common set of differential current sourced drivers.

Abstract: A digital phase-locked loop adjusts the phase of a Recovered Clock in the receiver under the condition of asynchronous serial data transmission so that the phases of the transmission data are locked in order to reduce errors in read data. The digital phase-locked loop includes a zero-phase start circuit, a phase-error detecting circuit, an error-filtering circuit, a Recovered Clock adjusting circuit and a clock-generation circuit. This phase-locked loop generates a set of clocks through the detection of the transmission data level in the zero-phase start circuit so as to lock the phase of the transmission data quickly, and the phase-error detecting circuit detects the phase error between the phase of the transmission data and the phase of the Recovered Clock, after which the phase error signal is filtered through the adaptive filtering circuit for conversion into error-adjusting signals.

Abstract: A digital phase-locked data recovery circuit having improved noise immunity. The data recovery circuit includes a multi-phase clock for supplying clock signals having a predetermined relative phase relationship. A snap shot sampling network takes samples of an input data signal in response to the multi-phase clock signals. The samples are preferably collected during the duration of boundary sampling windows encompassing transitions in the input data signal. The present invention further includes a network for comparing the received data samples with a sample pattern. A phase encoder then generates error signals in response to the phase comparisons. A phase decoder adjusts the phase of the boundary window in response to the error signal.

Abstract: A timing recovery scheme disposed to be substantially invariant to the specific composition of an input data sequence. The phase detection network of the present invention will typically be addressed by a data waveform having a plurality of data packets separated by data delimiters. In operation, the phase detection network of the present invention generates a phase error signal in response to the phase difference between a binary data waveform and a periodic clock waveform recovered therefrom. The inventive phase detection network includes a shift register for storing samples of the incident data waveform. The contents of the shift register are monitored by a boundary detection circuit disposed to signal the presence of one of the delimiters within the shift register. Upon detection of such a delimiter a boundary correction circuit is disposed to generate a phase detection enable signal.

Abstract: A multiphase clock generator which exhibits frequency stability in the presence of power supply noise. The clock generator of the present invention includes a phase detector for generating a phase error signal in response to the phase difference between an input signal and a recovered clock signal. A phase-locked feedback loop is operative to synthesize a recovered clock signal in response to the phase error signal. Included within the feedback loop is a differential ring oscillator disposed to provide first and second phase-shifted output signals at first and second output ports. The addition of a combination network to the multiphase clock generator of the present invention allows a multiplied clock signal to be derived from an input signal. Specifically, the phase-locked feedback loop 18 included within the clock multiplier of the present invention provides a plurality of sequentially phase-shifted waveforms at a first multiple of the frequency of the input signal.

Abstract: A method and apparatus for predistorting digital signals so as to minimize radiation of harmonic signal energy during data transmission. The programmable waveshaping apparatus of the present invention is operative to predistort a binary encoded waveform to be transmitted over a transmission line. A pulse discriminator circuit is disposed to indicate the receipt of each pulse within an input sequence of short and long pulses included within the encoded waveform. Upon receipt of each short and long pulse an input logic network generates first and second sets of control signals, respectively. The logic network synthesizes the control signals based on information relating to sampled approximations of filtered versions of the short and long pulses. The inventive waveshaping apparatus further includes a programmable electrical source array for generating a sequence of line driving signals in accordance with each set of control signals.