Abstract: A physical layer communication device (PHY) transmits and receives signal to and from a communication link using a synchronous protocol. The PHY communicates with a higher-layer device using a packet protocol. Timestamp values contained in timing-related messages in some packets are written or modified by the PHY. Delays incurred in transmitting and receiving the packets are predicted and used in setting the timestamp values.

Abstract: A physical layer communication device (PHY) transmits and receives signal to and from a communication link using a synchronous protocol. The PHY communicates with a higher-layer device using a packet protocol. Timestamp values contained in timing-related messages in some packets are written or modified by the PHY. Delays incurred in transmitting and receiving the packets are predicted and used in setting the timestamp values.

Abstract: A physical layer communication device (PHY) transmits and receives signal to and from a communication link using a synchronous protocol. The PHY communicates with a higher-layer device using a packet protocol. Timestamp values contained in timing-related messages in some packets are written or modified by the PHY. Delays incurred in transmitting and receiving the packets are predicted and used in setting the timestamp values.

Abstract: Device and methods determine timing parameters and associated timing actions from timing messages in communication packets. The timing messages may be encapsulated with plurality of communication protocols. An example timing message may be an IEEE 1588 timing message encapsulated in an Internet protocol packet encapsulated in an Ethernet protocol packet. The protocols are matched in classifier blocks by comparing portions of the packet to bit values or ranges of values. Operation of other than the first classifier block depends on results of matching in the preceding block by using offset values passed between blocks that indicate starting points for the matching. The final classifier block matches values in timing messages to identify timing parameters and associated timing actions in the message.

Abstract: Device and methods determine timing parameters and associated timing actions from timing messages in communication packets. The timing messages may be encapsulated with a plurality of communication protocols. An example timing message may be an IEEE 1588 timing message encapsulated in an Internet protocol packet encapsulated in an Ethernet protocol packet. The protocols are matched in classifier blocks by comparing portions of the packet to bit values or ranges of values. Operation of other than the first classifier block depends on results of matching in the preceding block by using offset values passed between blocks that indicate starting points for the matching. The final classifier block matches values in timing messages to identify timing parameters and associated timing actions in the message.

Abstract: A physical layer communication device (PHY) transmits and receives signal to and from a communication link using a synchronous protocol. The PHY communicates with a higher-layer device using a packet protocol. Timestamp values contained in timing-related messages in some packets are written or modified by the PHY. Delays incurred in transmitting and receiving the packets are predicted and used in setting the timestamp values.

Abstract: Device and methods determine timing parameters and associated timing actions from timing messages in communication packets. The timing messages may be encapsulated with plurality of communication protocols. An example timing message may be an IEEE 1588 timing message encapsulated in an Internet protocol packet encapsulated in an Ethernet protocol packet. The protocols are matched in classifier blocks by comparing portions of the packet to bit values or ranges of values. Operation of other than the first classifier block depends on results of matching in the preceding block by using offset values passed between blocks that indicate starting points for the matching. The final classifier block matches values in timing messages to identify timing parameters and associated timing actions in the message.

Abstract: An integrated circuit on which are implemented a number of devices that conform to the Rapidio network architecture. Included in the integrated circuit are two addressed RapidIO devices and switching devices which provide 24 switching ports. The devices have a packet receiving side and a packet transmitting side; the packet receiving side of each of the devices is connected by 128-bit wide paths termed poles its own packet transmitting side and each of the other transmitting sides. Features of the integrated circuit include centralized multicasting and configuration control for all of the devices on the integrated circuit, provisions for having more than one address in a RapidIO device, techniques for defining the address space routed by a routing table, techniques for managing congestion, and advanced buffer management techniques.

Abstract: An integrated circuit on which are implemented a number of devices that conform to the Rapidio network architecture. Included in the integrated circuit are two addressed RapidIO devices and switching devices which provide 24 switching ports. The devices have a packet receiving side and a packet transmitting side; the packet receiving side of each of the devices is connected by 128-bit wide paths termed poles its own packet transmitting side and each of the other transmitting sides. Features of the integrated circuit include centralized multicasting and configuration control for all of the devices on the integrated circuit, provisions for having more than one address in a RapidIO device, techniques for defining the address space routed by a routing table, techniques for managing congestion, and advanced buffer management techniques.

Abstract: An integrated circuit on which are implemented a number of devices that conform to the Rapidio network architecture. Included in the integrated circuit are two addressed RapidIO devices and switching devices which provide 24 switching ports. The devices have a packet receiving side and a packet transmitting side; the packet receiving side of each of the devices is connected by 128-bit wide paths termed poles its own packet transmitting side and each of the other transmitting sides. Features of the integrated circuit include centralized multicasting and configuration control for all of the devices on the integrated circuit, provisions for having more than one address in a RapidIO device, techniques for defining the address space routed by a routing table, techniques for managing congestion, and advanced buffer management techniques.