Abstract: A ductwork system including a duct having a plurality of ducting panels joined together to define a flow passage extending therethrough, and the duct having structure for resisting damage thereto caused by a detonation within the duct. The structure for resisting damage can include an internal bracing within and extending across the flow passage of the duct to tie at least two sides of the duct together. For example, the internal bracing can be a reinforcement panel including a mounting frame with one or more elongated members extending from one side of the frame attached to a ducting panel to another side of the frame attached to an opposite ducting panel. Alternatively or in addition to the above structure, the duct can have structure for resisting damage that includes providing the duct with at least one curved or faceted side along an axial length of the duct.

Abstract: A switching fabric having cross points that process multiple stripes of serial data. Each cross point includes a plurality of port slices and ports. Each port includes a plurality of FIFOs, a FIFO read arbitrator, a multiplexer, a dispatcher, and an accumulator. In one embodiment, each cross point has eight ports and eight port slices. A method for processing a stripe of data at a cross point at one port slice includes storing data received from other port slices in a plurality of FIFOs and arbitrating the reading of the stored data. A step of writing data received from a port at the one port slice to an appropriate FIFO in a different port slice is also included. In one embodiment, a method for processing data in port slice based on wide cell encoding and an external flow control command is provided.

Abstract: A switching fabric having cross points that process multiple stripes of serial data. Each cross point includes a plurality of port slices and ports. Each port includes a plurality of FIFOs, a FIFO read arbitrator, a multiplexer, a dispatcher, and an accumulator. In one embodiment, each cross point has eight ports and eight port slices. A method for processing a stripe of data at a cross point at one port slice includes storing data received from other port slices in a plurality of FIFOs and arbitrating the reading of the stored data. A step of writing data received from a port at the one port slice to an appropriate FIFO in a different port slice is also included. In one embodiment, a method for processing data in port slice based on wide cell encoding and an external flow control command is provided.

Abstract: A recycling apparatus for spent protective atmosphere gas contaminated with fouling organic decomposition byproduct materials. The recycling apparatus includes a compressor having an inlet connected to a spent protective atmosphere gas supply line, and a solvent supply configured to supply solvent to a gas passage at or upstream of the compressor. The recycling apparatus also includes a first chamber connected to an outlet of the compressor, where the first chamber is configured to receive compressed gas from the compressor and to collect a mixture including the solvent and any contaminants entrapped or dissolved in the solvent.

Abstract: A backplane interface adapter for a network switch. The backplane interface adapter includes at least one receiver that receives input cells carrying packets of data; at least one cell generator that generates encoded cells which include the packets of data from the input cells; and at least one transmitter that transmits the generated cells to a switching fabric. The cell includes a destination slot identifier that identifies a slot of the switching fabric towards which the respective input cell is being sent. The generated cells include in-band control information.

Abstract: A backplane interface adapter for a high-performance network switch. The backplane interface adapter receives narrow input cells carrying packets of data and outputs wide striped cells to a switching fabric. One traffic processing path through the backplane interface adapter includes deserializer receivers, a traffic sorter, wide cell generators, stripe send queues, a backplane transmit arbitrator, and serializer transmitters. Another traffic processing path through the backplane interface adapter includes deserialize receivers, a stripe interface, stripe receive synchronization queues, a controller, wide/narrow cell translator, destination queues, and serializer transmitters. An encoding scheme for packets of data carried in wide striped cells is provided.

Abstract: A computer. When an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location is recognized, a value is stored representative of an architecturally-visible representation of the side-effect, a format of the representative value being different than an architecturally-visible representation of the side-effect. Execution is resumed without generating the architecturally-visible side-effect. Later, the architecturally-visible representation corresponding to the representative value is written into the architecturally-visible storage location. On a context switch, a context of a first process is written and a context of a second process is loaded to place the second process into execution. At least some instructions maintain results in storage resources outside the context resource set, and instructions are marked to indicate whether or not a context switch may be performed at a boundary of the marked instruction.

Abstract: The present invention provides a high-performance network switch. A digital switch has a plurality of blades coupled to a switching fabric via serial pipes. Serial link technology is used in the switching fabric. Each blade outputs serial data streams with in-band control information in multiple stripes to the switching fabric. The switching fabric includes a plurality of cross points corresponding to the multiple stripes. In one embodiment five stripes and five cross points are used. Each blade has a backplane interface adapter (BIA). One or more integrated bus translators (IBTs) and/or source packet processors are coupled to a BIA. An encoding scheme for packets of data carried in wide striped cells is provided.

Abstract: A system and method for encoding wide striped cells that carry packets of data across stripes. The method encodes an initial block of a first wide striped cell is encoded with initial cell encoding information, and distributes initial bytes of packet data into available space in the initial block of the first wide striped cell. The initial cell encoding information includes control information and state information. One initial block of the first wide striped cell comprises five subblocks corresponding to five stripes. Each subblock includes identical control information and identical state information. The method further includes adding reserve information to available bytes at the end of the initial block of the first wide striped cell. Remaining bytes of packet data are distributed across one or more blocks in the first wide striped cell until an end of packet condition is reached or a maximum cell size is reached.

Abstract: The present invention provides a high-performance network switch. A digital switch has a plurality of blades coupled to a switching fabric via serial pipes. Serial link technology is used in the switching fabric. Each blade outputs serial data streams with in-band control information in multiple stripes to the switching fabric. The switching fabric includes a plurality of cross points corresponding to the multiple stripes. In one embodiment five stripes and five cross points are used. Each blade has a backplane interface adapter (BIA). One or more integrated bus translators (IBTs) and/or source packet processors are coupled to a BIA. An encoding scheme for packets of data carried in wide striped cells is provided.

Abstract: A system and method for encoding wide striped cells that carry packets of data across stripes. The method encodes an initial block of a first wide striped cell is encoded with initial cell encoding information, and distributes initial bytes of packet data into available space in the initial block of the first wide striped cell. The initial cell encoding information includes control information and state information. One initial block of the first wide striped cell comprises five subblocks corresponding to five stripes. Each subblock includes identical control information and identical state information. The method further includes adding reserve information to available bytes at the end of the initial block of the first wide striped cell. Remaining bytes of packet data are distributed across one or more blocks in the first wide striped cell until an end of packet condition is reached or a maximum cell size is reached.

Abstract: A system and method for encoding wide striped cells that carry packets of data across stripes. The method encodes an initial block of a first wide striped cell is encoded with initial cell encoding information, and distributes initial bytes of packet data into available space in the initial block of the first wide striped cell. The initial cell encoding information includes control information and state information. One initial block of the first wide striped cell comprises five subblocks corresponding to five stripes. Each subblock includes identical control information and identical state information. The method further includes adding reserve information to available bytes at the end of the initial block of the first wide striped cell. Remaining bytes of packet data are distributed across one or more blocks in the first wide striped cell until an end of packet condition is reached or a maximum cell size is reached.

Abstract: The present invention provides a high-performance network switch. A digital switch has a plurality of blades coupled to a switching fabric via serial pipes. Serial link technology is used in the switching fabric. Each blade outputs serial data streams with in-band control information in multiple stripes to the switching fabric. The switching fabric includes a plurality of cross points corresponding to the multiple stripes. In one embodiment five stripes and five cross points are used. Each blade has a backplane interface adapter (BIA). One or more integrated bus translators (IBTs) and/or source packet processors are coupled to a BIA. An encoding scheme for packets of data carried in wide striped cells is provided.

Abstract: A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.

Abstract: A backplane interface adapter for a high-performance network switch. The backplane interface adapter receives narrow input cells carrying packets of data and outputs wide striped cells to a switching fabric. One traffic processing path through the backplane interface adapter includes deserializer receivers, a traffic sorter, wide cell generators, stripe send queues, a backplane transmit arbitrator, and serializer transmitters. Another traffic processing path through the backplane interface adapter includes deserialize receivers, a stripe interface, stripe receive synchronization queues, a controller, wide/narrow cell translator, destination queues, and serializer transmitters. An encoding scheme for packets of data carried in wide striped cells is provided.

Abstract: A switching fabric having cross points that process multiple stripes of serial data. Each cross point includes a plurality of port slices and ports. Each port includes a plurality of FIFOs, a FIFO read arbitrator, a multiplexer, a dispatcher, and an accumulator. In one embodiment, each cross point has eight ports and eight port slices. A method for processing a stripe of data at a cross point at one port slice includes storing data received from other port slices in a plurality of FIFOs and arbitrating the reading of the stored data. A step of writing data received from a port at the one port slice to an appropriate FIFO in a different port slice is also included. In one embodiment, a method for processing data in port slice based on wide cell encoding and an external flow control command is provided.

Abstract: The present invention provides a high-performance network switch. A digital switch has a plurality of blades coupled to a switching fabric via serial pipes. Serial link technology is used in the switching fabric. Each blade outputs serial data streams with in-band control information in multiple stripes to the switching fabric. The switching fabric includes a plurality of cross points corresponding to the multiple stripes. In one embodiment five stripes and five cross points are used. Each blade has a backplane interface adapter (BIA). One or more integrated bus translators (IBTs) and/or source packet processors are coupled to a BIA. An encoding scheme for packets of data carried in wide striped cells is provided.

Abstract: A system and method for encoding wide striped cells that carry packets of data across stripes. The method encodes an initial block of a first wide striped cell is encoded with initial cell encoding information, and distributes initial bytes of packet data into available space in the initial block of the first wide striped cell. The initial cell encoding information includes control information and state information. One initial block of the first wide striped cell comprises five subblocks corresponding to five stripes. Each subblock includes identical control information and identical state information. The method further includes adding reserve information to available bytes at the end of the initial block of the first wide striped cell. Remaining bytes of packet data are distributed across one or more blocks in the first wide striped cell until an end of packet condition is reached or a maximum cell size is reached.

Abstract: An IPC/IGC Bus Translator (IBT) translates between data formats including packets and narrow cells. IBT processes received packets, parsing them into cells or one or more cell formats. The invention is a system and method that selects the appropriate cell format based on predetermined factors. In one embodiment, the topology and configuration of the IPC/IGC components are factors used to determine the appropriate cell format. In another embodiment, the IBT receives cells and processes the received cells into packets. In one embodiment, the IBT translates packets receives in a parallel architecture into cells in a serial architecture. The translator operates with packets in a parallel configuration and narrow cells in a serial configuration. A narrow cell format has a header and payload. The header includes a special character and control information. The payload includes data.