Abstract: Methods, systems, and apparatus for handling applications in an ambient computing system. One of the apparatus includes multiple devices arranged in multiple power blocks, wherein each device of the multiple devices belongs to one of the multiple power blocks; and multiple local power managers, each local power manager being programmable to execute respective sets of instruction sequences for a respective power block in order to effectuate power state transitions for one or more devices in the respective power block.

Abstract: A method for serial interface clock domain crossing includes identifying a data communication command received over a serial interface. An address is decoded to determine whether the address falls within a direct latch address range of a register bank. Data is communicated over the serial interface. A multiplexed output clock is generated, for writing to and reading from the register bank, based on at least one of a current system operating state and a refresh control signal from a host processor.

Abstract: A method for serial interface clock domain crossing includes identifying a data communication command received over a serial interface. An address is decoded to determine whether the address falls within a direct latch address range of a register bank. Data is communicated over the serial interface. A multiplexed output clock is generated, for writing to and reading from the register bank, based on at least one of a current system operating state and a refresh control signal from a host processor.

Abstract: Aspects of a clock domain crossing serial interface, direct latching over the serial interface, and response codes are described. In various embodiments, a data communication command received over a serial interface is identified, and an address received over the serial interface is resolved to access a register bank. In a write operation, depending upon whether the address falls within a direct latch address range of the register bank, data may be directly latched into a direct latch register of the register bank or into a first-in-first-out register. For both read and write operations, reference may be made to a status register of the serial interface to identify or mitigate error conditions, and wait times may be relied upon to account for a clock domain crossing. After each of the read and write operations, a response code including a status indictor may be communicated.

Abstract: Aspects of power and system management information visibility are described. In various embodiments, a system parameter of a system is measured. The system parameter may include one or more parameters such as system voltages, temperatures, options, or conditions of the system. The system parameter may be evaluated by a power manager processor. The evaluation may determine operating settings for one or more elements of the system. Based on the evaluation, one or more operating parameters for elements of the system may be set, in advance of powering up the system elements. After the operating parameters have been set, system elements may be released to start or boot based on the operating parameters. In this manner, one or more elements of the system may power on in a more flexible and deliberate manner, taking the current operating environment of the system into consideration.

Abstract: Aspects of a clock domain crossing serial interface, direct latching over the serial interface, and response codes are described. In various embodiments, a data communication command received over a serial interface is identified, and an address received over the serial interface is resolved to access a register bank. In a write operation, depending upon whether the address falls within a direct latch address range of the register bank, data may be directly latched into a direct latch register of the register bank or into a first-in-first-out register. For both read and write operations, reference may be made to a status register of the serial interface to identify or mitigate error conditions, and wait times may be relied upon to account for a clock domain crossing. After each of the read and write operations, a response code including a status indictor may be communicated.