Abstract: A method is provided for packet flow control for a switching node of a data transfer network. The method includes actively managing space allocations in a central queue of a switching node allotted to the ports of the switching node based on the amount of unused space currently available in the central queue. In a further aspect, the method includes separately tracking unallocated space and vacated allocated space, which had been used to buffer packets received by the ports but were vacated since a previous management update due to a packet being removed from the central queue. Each port is offered vacated space that is currently allocated to that port and a quantity of the currently unallocated space in the central queue to distribute to one or more virtual lanes of the port.

Abstract: A method is provided for packet flow control for a switching node of a data transfer network. The method includes actively managing space allocations in a central queue of a switching node allotted to the ports of the switching node based on the amount of unused space currently available in the central queue. In a further aspect, the method includes separately tracking unallocated space and vacated allocated space, which had been used to buffer packets received by the ports but were vacated since a previous management update due to a packet being removed from the central queue. Each port is offered vacated space that is currently allocated to that port and a quantity of the currently unallocated space in the central queue to distribute to one or more virtual lanes of the port.

Abstract: Method, system and program product are provided for packet flow control for a switching node of a data transfer network. The method includes actively managing space allocations in a central queue of a switching node allotted to the ports of the switching node based on the amount of unused space currently available in the central queue. In a further aspect, the method includes separately tracking unallocated space and vacated allocated space, which had been used to buffer packets received by the ports but were vacated since a previous management update due to a packet being removed from the central queue. Each port is offered vacated space that is currently allocated to that port and a quantity of the currently unallocated space in the central queue to distribute to one or more virtual lanes of the port.

Abstract: A technique is provided for simultaneous and/or selective self-testing of internal logic and asynchronous boundaries of an IC having a plurality of clock domains. A clock command is generated by an on product clock generator for each clock domain simultaneously; and an asynchronous receive clock driver provides a programmable delay to a capture clock based on predetermined cycle requirements of the asynchronous boundaries. Asynchronous boundary test requirements are defined exclusively from the perspective of the asynchronous boundary receiver latches, thereby reducing dependencies among clock domains. Advantageously, the design of internal logic and asynchronous boundaries of each clock domain, ultimately residing within an IC, can proceed without a priori knowledge of how the clock domain will eventually be used in aggregation with other clock domains.

Abstract: Method, system and program product are provided for packet flow control for a switching node of a data transfer network. The method includes actively managing space allocations in a central queue of a switching node allotted to the ports of the switching node based on the amount of unused space currently available in the central queue. In a further aspect, the method includes separately tracking unallocated space and vacated allocated space, which had been used to buffer packets received by the ports but were vacated since a previous management update due to a packet being removed from the central queue. Each port is offered vacated space that is currently allocated to that port and a quantity of the currently unallocated space in the central queue to distribute to one or more virtual lanes of the port.

Abstract: A technique is provided for simultaneous and/or selective self-testing of internal logic and asynchronous boundaries of an IC having a plurality of clock domains. A clock command is generated by an on product clock generator for each clock domain simultaneously; and an asynchronous receive clock driver provides a programmable delay to a capture clock based on predetermined cycle requirements of the asynchronous boundaries. Asynchronous boundary test requirements are defined exclusively from the perspective of the asynchronous boundary receiver latches, thereby reducing dependencies among clock domains. Advantageously, the design of internal logic and asynchronous boundaries of each clock domain, ultimately residing within an IC, can proceed without a priori knowledge of how the clock domain will eventually be used in aggregation with other clock domains.