Patents by Inventor Ronald A. Weimer

Ronald A. Weimer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11257838
    Abstract: Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: February 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Ronald A. Weimer, Kyu S. Min, Thomas M. Graettinger, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20200203360
    Abstract: Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.
    Type: Application
    Filed: February 27, 2020
    Publication date: June 25, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Ronald A. Weimer, Kyu S. Min, Thomas M. Graettinger, Durai Vishak Nirmal Ramaswamy
  • Patent number: 10608005
    Abstract: Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ronald A. Weimer, Kyu S. Min, Thomas M. Graettinger, Durai Vishak Nirmal Ramaswamy
  • Patent number: 9424226
    Abstract: Method and system for performing an equalization process between a remote PCI (Peripheral Component Interface)-Express device and a local PCI-Express device are provided. The use of a forced coefficient in a third phase of the equalization process is enabled. When the remote PCI-Express has made a preset request, then the local PCI-Express device sends the preset request back to the remote PCI-Express device with the forced coefficient.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: August 23, 2016
    Assignee: QLOGIC, Corporation
    Inventor: Ronald A. Weimer
  • Patent number: 9397210
    Abstract: A memory array has first and second memory cells over a semiconductor and an isolation region extending into the semiconductor. The isolation region includes an air gap between charge-storage structures of the first and second memory cells and a thickness of dielectric over the air gap and contained between the first and second memory cells.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: July 19, 2016
    Assignee: Micron Technology, Inc.
    Inventors: James Mathew, Gordon Haller, Ronald A. Weimer, John Hopkins, Vinayak K. Shamanna, Sanjeev Sapra
  • Patent number: 9311268
    Abstract: Methods and systems for ignoring protocol defined framing errors at a peripheral device coupled to a processor via an interconnect system are provided. When a framing error violation does not affect data transfer to the peripheral device or from the peripheral device, the protocol defined link training sequence is disabled to ignore the framing error and the peripheral device continues to process data regardless of the framing error.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: April 12, 2016
    Assignee: QLOGIC, Corporation
    Inventors: Qian Chen, Ronald A. Weimer
  • Patent number: 9082714
    Abstract: Embodiments of the present disclosure are directed towards use of an etch process post wordline definition to improve data retention in a flash memory device. In one embodiment, a method includes forming a plurality of wordline structures on a substrate, wherein individual wordline structures of the plurality of wordline structures include a control gate having an electrically conductive material and a cap having an electrically insulative material formed on the control gate, depositing an electrically insulative material to form a liner on a surface of the individual wordline structures, and etching the liner to remove at least a portion of the liner. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: July 14, 2015
    Assignee: Intel Corporation
    Inventors: Randy J. Koval, Max F. Hineman, Ronald A. Weimer, Vinayak K. Shamanna, Thomas M. Graettinger, William R. Kueber, Christopher Larsen, Alex J. Schrinsky
  • Publication number: 20140027832
    Abstract: A memory array has first and second memory cells over a semiconductor and an isolation region extending into the semiconductor. The isolation region includes an air gap between charge-storage structures of the first and second memory cells and a thickness of dielectric over the air gap and contained between the first and second memory cells.
    Type: Application
    Filed: October 2, 2013
    Publication date: January 30, 2014
    Applicant: Micron Technology, Inc.
    Inventors: James Mathew, Gordon Haller, Ronald A. Weimer, John Hopkins, Vinayak K. Shamanna, Sanjeev Sapra
  • Patent number: 8569130
    Abstract: Methods of forming air gaps in memory arrays and memory arrays with air gaps thus formed are disclosed. One such method may include forming an isolation region, having a first dielectric, through a charge-storage structure that is over a semiconductor, the isolation region extending into the semiconductor; forming a second dielectric over the isolation region and charge-storage structure; and forming an air gap in the isolation region so that the air gap passes through the charge-storage structure and so that a thickness of the first dielectric is between the air gap and the second dielectric.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: October 29, 2013
    Assignee: Micron Technology, Inc.
    Inventors: James Mathew, Gordon Haller, Ronald A. Weimer, John Hopkins, Vinayak K. Shamanna, Sanjeev Sapra
  • Publication number: 20130264628
    Abstract: Embodiments of the present disclosure describe techniques and configurations relating to use of an etch process post wordline definition to improve data retention in a flash memory device. In one embodiment, a method includes forming a plurality of wordline structures on a substrate, wherein individual wordline structures of the plurality of wordline structures include a control gate having an electrically conductive material and a cap having an electrically insulative material formed on the control gate, depositing an electrically insulative material to form a liner on a surface of the individual wordline structures, and etching the liner to remove at least a portion of the liner. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 22, 2011
    Publication date: October 10, 2013
    Inventors: Randy J. Koval, Max F. Hineman, Ronald A. Weimer, Vinayak K. Shamanna, Thomas M. Graettinger, William R. Kueber, Christopher Larsen, Alex J. Schrinsky
  • Patent number: 8518184
    Abstract: The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: August 27, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Kevin L. Beaman, Trung T. Doan, Lyle D. Breiner, Ronald A. Weimer, Er-Xuan Ping, David J. Kubista, Cem Basceri, Lingyi A. Zheng
  • Patent number: 8384192
    Abstract: The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 ?.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: February 26, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Lingyi A. Zheng, Trung T. Doan, Lyle D. Breiner, Er-Xuan Ping, Kevin L. Beaman, Ronald A. Weimer, Cem Basceri, David J. Kubista
  • Publication number: 20130026600
    Abstract: Methods of forming air gaps in memory arrays and memory arrays with air gaps thus formed are disclosed. One such method may include forming an isolation region, having a first dielectric, through a charge-storage structure that is over a semiconductor, the isolation region extending into the semiconductor; forming a second dielectric over the isolation region and charge-storage structure; and forming an air gap in the isolation region so that the air gap passes through the charge-storage structure and so that a thickness of the first dielectric is between the air gap and the second dielectric.
    Type: Application
    Filed: July 28, 2011
    Publication date: January 31, 2013
    Inventors: James Matthew, Gordon Haller, Ronald A. Weimer, John Hopkins, Vinayak K. Shamanna, Sanjeev Sapra
  • Patent number: 8294192
    Abstract: A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. Additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. The interface can be formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability. Oxide in an upper storage dielectric layer is enhanced in the dilute steam oxidation. The thin oxide layers serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: October 23, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Ronald A. Weimer, Don C. Powell, John T. Moore, Jeff A. McKee
  • Patent number: 8228743
    Abstract: Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: July 24, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Kyu S. Min, Rhett T. Brewer, Tejas Krishnamohan, Thomas M. Graettinger, D. V. Nirmal Ramaswamy, Ronald A Weimer, Arup Bhattacharyya
  • Patent number: 8153502
    Abstract: Methods of filling cavities or trenches. More specifically, methods of filling a cavity or trench in a semiconductor layer are provided. The methods include depositing a first dielectric layer into the trench by employing a conformal deposition process. Next, the first dielectric layer is etched to create a recess in the trench within the first dielectric layer. The recesses are then filled with a second dielectric layer by employing a high density plasma deposition process. The techniques may be particularly useful in filling cavities and trenches having narrow widths and/or high aspect ratios.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: April 10, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Li Li, Ronald Weimer, Richard Stocks, Chris Hill
  • Patent number: 8119483
    Abstract: Some embodiments include methods of utilizing polysilazane in forming non-volatile memory cells. The memory cells may be multi-level cells (MLCs). The polysilazane may be converted to silicon nitride, silicon dioxide, or silicon oxynitride with thermal processing and exposure to an ambient that contains one or both of oxygen and nitrogen. The methods may include using the polysilazane in forming a charge trapping layer of a non-volatile memory cell. The methods may alternatively, or additionally include using the polysilazane in forming intergate dielectric material of a non-volatile memory cell. Some embodiments include methods of forming memory cells of a NAND memory array.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: February 21, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Ronald A. Weimer
  • Publication number: 20110254075
    Abstract: A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. Additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. The interface can be is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability. Oxide in an upper storage dielectric layer is enhanced in the dilute steam oxidation. The thin oxide layers serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.
    Type: Application
    Filed: June 24, 2011
    Publication date: October 20, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Ronald A. Weimer, Don C. Powell, John T. Moore, Jeff A. McKee
  • Patent number: 7989870
    Abstract: A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. Additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. The interface can be formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability. Oxide in an upper storage dielectric layer is enhanced in the dilute steam oxidation. The thin oxide layers serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: August 2, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Ronald A Weimer, Don C Powell, John T Moore, Jeff A McKee
  • Publication number: 20110163416
    Abstract: The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 ?.
    Type: Application
    Filed: March 14, 2011
    Publication date: July 7, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Lingyi A. Zheng, Trung T. Doan, Lyle D. Breiner, Er-Xuan Ping, Kevin L. Beaman, Ronald A. Weimer, Cem Basceri, David J. Kubista