Abstract: A digital data and clock recovery circuit for use in a digital test head has a digital input port and a digital output port. A clock having a frequency several times the nominal bit rate of the input data drives several series-connected flip flops to generate a corresponding output pulse stream in which the pulses are of fixed pulse duration. Outputs are also taken from the flip flop array to generate a strobe pulse having a predetermined phase relationship to the output data pulses. The flip flop array operates on positive going pulses derived from a bipolar data input stream. An identical array is used to similarly condition negative going input data pulses, outputs from the arrays being combined to synchronize the strobe signal.