Abstract: A power supply circuit can be configured to include a first circuit and a second circuit. Each circuit can be substantially identical to each other but provide different functionality depending on how they are configured. For example, each of the first circuit and second circuit can be chips having substantially the same pin layout and internal circuitry. However, the functionality provided by the circuits varies depending on whether a respective circuit is configured as a master or slave. The first circuit is configured as the master and generates multiple phase control signals. The first circuit uses a portion of the multiple phase control signals to control a first set of phases. The first circuit transmits a second portion of the multiple phase control signals to the second circuit configured as a slave. The second circuit is configured to receive and use the second portion of control signals to control a second set of phases.

Abstract: One configuration of the present disclosure is directed to a switch driver circuit. The switch driver circuit can include an input to receive a control signal; an output to control a state of an switch in accordance with the control signal; and a set of parallel switches. The set of parallel switches in the switch driver circuit includes a P-type field effect transistor in parallel with an N-type field effect transistor. During operation, via variations in the control signal, the control signal selectively and electrically couples a voltage source signal to the output of the switch driver circuit to control the state of the switch.

Abstract: A power supply circuit can be configured to include a first circuit and a second circuit. Each circuit can be substantially identical to each other but provide different functionality depending on how they are configured. For example, each of the first circuit and second circuit can be chips having substantially the same pin layout and internal circuitry. However, the functionality provided by the circuits varies depending on whether a respective circuit is configured as a master or slave. The first circuit is configured as the master and generates multiple phase control signals. The first circuit uses a portion of the multiple phase control signals to control a first set of phases. The first circuit transmits a second portion of the multiple phase control signals to the second circuit configured as a slave. The second circuit is configured to receive and use the second portion of control signals to control a second set of phases.

Abstract: A technique that is readily implemented in monolithic integrated circuits includes a phase-locked loop (PLL) that generates an output clock signal based on a reference clock signal and selectable configuration parameters. A method includes providing to a PLL circuit, selected configuration information based, at least in part, on a selected frequency of a reference clock signal and a selected PLL bandwidth. The method includes generating an output clock signal, by the PLL circuit, based, at least in part, on the reference clock signal and the selected configuration information. The method includes storing in a storage circuit, a plurality of sets of configuration information corresponding to a range of frequencies of the reference clock signal and a range of PLL bandwidths. The selected configuration information is accessed from the plurality of sets of configuration information according to the selected frequency and the selected bandwidth.

Abstract: A technique that is readily implemented in monolithic integrated circuits reduces or eliminates phase glitches when switching between input reference clock signals. The technique combines a pulsed phase-difference signal and a pulsed phase-difference compensation signal to substantially attenuate a DC component of the phase-difference signal and at least partially attenuate harmonic components of the phase-difference signal. The pulsed phase-difference compensation signal is based on an indicator of a phase difference between the input reference clock signals.

Abstract: A technique that is readily implemented in monolithic integrated circuits reduces or eliminates phase glitches when switching between input reference clock signals. The technique combines a pulsed phase-difference signal and a pulsed phase-difference compensation signal to substantially attenuate a DC component of the phase-difference signal and at least partially attenuate harmonic components of the phase-difference signal. The pulsed phase-difference compensation signal is based on an indicator of a phase difference between the input reference clock signals.

Abstract: A technique that is readily implemented in monolithic integrated circuits includes a phase-locked loop (PLL) that generates an output clock signal based on a reference clock signal and selectable configuration parameters. A method includes providing to a PLL circuit, selected configuration information based, at least in part, on a selected frequency of a reference clock signal and a selected PLL bandwidth. The method includes generating an output clock signal, by the PLL circuit, based, at least in part, on the reference clock signal and the selected configuration information. The method includes storing in a storage circuit, a plurality of sets of configuration information corresponding to a range of frequencies of the reference clock signal and a range of PLL bandwidths. The selected configuration information is accessed from the plurality of sets of configuration information according to the selected frequency and the selected bandwidth.

Abstract: A locking range of a current mode logic (CML) frequency divider circuit is tunable by dynamically adjusting a tail current of the frequency divider circuit according to a control signal. The control signal may be based on at least one control signal coupled to tune a controllable oscillator. The control signal may be based on a frequency of an output of a voltage controlled oscillator coupled to the frequency divider. The control signal may be based on the voltage swing of an output of a voltage controlled oscillator coupled to the frequency divider. The control signal may be based on an output of the frequency divider circuit.

Abstract: An ESD protective triggering circuit for a triggering circuit for a solid state ESD protective device. The arrangement is to provide a controlled current to the protective device that triggers the device so that the device snaps-back and additionally the triggering device enables the parasitic transistor to participate in the draining of the ESD current. The triggering circuit also terminates the current to the protective device when the ESD voltage starts to fall. The triggering circuit can be used in any computer controlled electronics system.

Abstract: A voltage controlled oscillator circuit is shown using multiple delay stages with the last stage looped back out of phase to the first stage. Each stage delay is formed by charging one or more capacitors. The circuitry uses active components demonstrating a square law relationship between a control voltage and a resulting current. The current is ultimately used to charge the delay capacitor. The net effect is a linear relationship of the VCO frequency and an input control voltage. The range of the linear relationship is extended by using square law current sources to provide suitable currents that extend the linear range when other active devices are no longer supporting the square law relationship. In addition bipolar device are used to compensate for temperature and batch to batch processing effects of FET devices.

Abstract: A phase locked loop, PLL, is described with multiple parallel charge pumps that are selectively disabled as phase lock is approached. A lock detection circuit is described that enabled reference currents to be fed to the parallel charge pumps. The error signal from a phase detector is arranged as UP and a DOWN signals that are averaged in the lock detector. When the average error is large, all the reference currents feed the charge pumps that provide a high loop gain to reduce the lock time. As the lock becomes closer selective reference currents are disabled to reduce loop gain so that a smooth transition to lock is made. Selectively switching currents into a low pass filter that usually follows a charge pump in a PLL circuit automatically reduces switching noise by the operation of the low pass filter.

Abstract: A structure of and a method for making an isolated NMOS transistor using standard BiCMOS processing steps and techniques. No additional masks and processing steps are needed for the isolated NMOS device relative to the standard process flow. A P-type substrate with an overlaying buried N-type layer overlaid with a buried p-type layer below a P-well is shown. An N-type region surrounds and isolates the P-well from other devices on the same wafer. N+ regions are formed in the p-well for the source and drain connections and poly or other such electrical conductors are formed on the gate, drain and source structures to make the NMOS device operational. Parasitic bipolar transistors are managed by the circuit design, current paths and biasing to ensure the parasitic bipolar transistors do not turn on.

Abstract: A current boost circuit that supplies additional current to a voltage reference power rail. When the voltage reference power rail drops due to an excessive current demand from the load, the drop is sensed and a switch is activated supplying additional current to the voltage reference rail. A gain stage is capacitively coupled to the reference voltage and any drop is transferred through this capacitor to a gain stage that amplifies the drop. The amplified drop is capacitively coupled to a solid state switch that turns on connecting an additional current source to the reference voltage rail. The solid state switch is biased just below its turn on threshold.

Abstract: An ESD NMOS structure with an odd number of N-type structures built into a P-type well. Buried N-type structures are positioned between the N-type structures. The center N-type structure and each alternate N-type structure are electrically connected to each other, to the buried N-type structures, and to the output contact; while the other N-type structures are electrically connected to each other and the P-well and to ground. When a positive ESD event occurs, a depletion zone is created in the P-well between the N-type buried structures and the N-type structures thereby increasing the resistivity of the structure. Moreover, when a positive ESD event occurs, the lateral NPN transistors on either side of the center N-type structure break down and snap back. The resulting current travels through the area of increased resistivity and thereby creates a larger voltage along the P-well from the center N-type structure out toward the distal N-type structures.

Abstract: A phase locked loop circuit is used to provide timing clocks for data bit recovery from a serial data flow. The system locks to a SYNC signal, preferably a lower frequency fifty percent duty cycle square wave with a period equal to the time of a fully framed serial data word. When a start signal transition is detected the system is prevented from trying to lock onto the data signal edge transitions. But, the system provides a signal suitable for clocking in the individual data bits.

Abstract: A voltage controlled oscillator circuit is shown using multiple delay stages with the last stage looped back out of phase to the first stage. Each stage delay is formed by charging one or more capacitors. The circuitry uses active components demonstrating a square law relationship between a control voltage and a resulting current. The current is ultimately used to charge the delay capacitor. The net effect is a linear relationship of the VCO frequency and an input control voltage. The range of the linear relationship is extended by using square law current sources to provide suitable currents that extend the linear range when other active devices are no longer supporting the square law relationship. In addition bipolar device are used to compensate for temperature and batch to batch processing effects of FET devices.

Abstract: A phase locked loop, PLL, is described with multiple parallel chnrge pumps that are selectively disabled as phase lock is approached. A lock detection circuit is described that enabled reference currents to be fed to the parallel charge pumps. The error signal from a phase detector is arranged as UP and a DOWN signals that are averaged in the lock detector. When the average error is large, all the reference currents feed the charge pumps that provide a high loop gain to reduce the lock time. As the lock becomes closer selective reference currents are disabled to reduce loop gain so that a smooth transition to lock is made. Selectively switching currents into a low pass filter that usually follows a charge pump in a PLL circuit automatically reduces switching noise by the operation of the low pass filter.

Abstract: A current boost circuit that supplies additional current to a voltage reference power rail. When the voltage reference power rail drops due to an excessive current demand from the load, the drop is sensed and a switch is activated supplying additional current to the voltage reference rail. A gain stage is capacitively coupled to the reference voltage and any drop is transferred through this capacitor to a gain stage that amplifies the drop. The amplified drop is capacitively coupled to a solid state switch that turns on connecting an additional current source to the reference voltage rail. The solid state switch is biased just below its turn on threshold.

Abstract: A phase locked loop circuit is used to provide timing clocks for data bit recovery from a serial data flow. The system locks to a SYNC signal, preferably a lower frequency fifty percent duty cycle square wave with a period equal to the time of a fully framed serial data word. When a start signal transition is detected the system is prevented from trying to lock onto the data signal edge transitions. But, the system provides a signal suitable for clocking in the individual data bits.

Abstract: An ESD NMOS structure with an odd number of N-type structures built into a P-type well. Buried N-type structures are positioned between the N-type structures. The center N-type structure and each alternate N-type structure are electrically connected to each other, to the buried N-type structures, and to the output contact; while the other N-type structures are electrically connected to each other and the P-well and to ground. When a positive ESD event occurs, a depletion zone is created in the P-well between the N-type buried structures and the N-type structures thereby increasing the resistivity of the structure. Moreover, when a positive ESD event occurs, the lateral NPN transistors on either side of the center N-type structure break down and snap back. The resulting current travels through the area of increased resistivity and thereby creates a larger voltage along the P-well from the center N-type structure out toward the distal N-type structures.