Patents by Inventor Ronald Barbee

Ronald Barbee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070138611
    Abstract: A package includes a device and a package substrate. The device includes a plurality of electrical pads, and has a periphery that defines a footprint. The package substrate, further includes a first substrate surface to which the device is attached, a second substrate surface, and a set of electrical contacts attached to the second substrate surface.
    Type: Application
    Filed: December 20, 2005
    Publication date: June 21, 2007
    Inventors: Ronald Barbee, Glenn Robertson, Robert Peene
  • Patent number: 6523123
    Abstract: The present invention is an apparatus and method for providing power management apparatus for a circuit in a processor-based system. The apparatus comprises a memory to store instruction sequences by which the processor-based system is processed and a processor coupled to the memory. The stored instruction sequences cause the processor to: (a) determine a system access time of the circuit; (b) determine if the system access time is less than a first predetermined value, if so, increasing an accessibility period of the circuit, during which the circuit is active. Various embodiments are described.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: February 18, 2003
    Assignee: Phoenix Technologies Ltd.
    Inventor: Ronald Barbee
  • Patent number: 6347377
    Abstract: The present invention is an apparatus and method for providing power management apparatus for a circuit in a processor-based system. The apparatus comprises a memory to store instruction sequences by which the processor-based system is processed and a processor coupled to the memory. The stored instruction sequences cause the processor to: (a) determine a system access time of the circuit; (b) determine if the system access time is less than a first predetermined value, if so, increasing an accessibility period of the circuit, during which the circuit is active. Various embodiments are described.
    Type: Grant
    Filed: November 4, 1998
    Date of Patent: February 12, 2002
    Assignee: Phoenix Technologies Ltd.
    Inventor: Ronald Barbee
  • Publication number: 20010047490
    Abstract: The present invention is an apparatus and method for providing power management apparatus for a circuit in a processor-based system. The apparatus comprises a memory to store instruction sequences by which the processor-based system is processed and a processor coupled to the memory. The stored instruction sequences cause the processor to: (a) determine a system access time of the circuit; (b) determine if the system access time is less than a first predetermined value, if so, increasing an accessibility period of the circuit, during which the circuit is active. Various embodiments are described.
    Type: Application
    Filed: July 27, 2001
    Publication date: November 29, 2001
    Inventor: Ronald Barbee
  • Publication number: 20010011315
    Abstract: The present invention is an apparatus and method for providing power management apparatus for a circuit in a processor-based system. The apparatus comprises a memory to store instruction sequences by which the processor-based system is processed and a processor coupled to the memory. The stored instruction sequences cause the processor to: (a) determine a system access time of the circuit; (b) determine if the system access time is less than a first predetermined value, if so, increasing an accessibility period of the circuit, during which the circuit is active. Various embodiments are described.
    Type: Application
    Filed: November 4, 1998
    Publication date: August 2, 2001
    Inventor: RONALD BARBEE