Abstract: Systems and methods for improving the timing alignment of non-overlapping waveforms are provided. In this regard, a representative system, among others, includes a waveform synthesizer that generates a plurality of input waveforms and inverters having inputs and outputs, wherein the inverters receive the input waveforms at the inputs of the inverters and invert the input waveforms, producing a plurality of inverted waveforms at the outputs of the inverters. The system also includes NOR gates having inputs and outputs, wherein the NOR gates receive the plurality of inverted waveforms at the inputs of the NOR gates and pass through one of the inverted waveforms at the outputs of the NOR gates.

Abstract: Systems and methods for improving the timing alignment of non-overlapping waveforms are provided. In this regard, a representative system, among others, includes a waveform synthesizer that generates a plurality of input waveforms and inverters having inputs and outputs, wherein the inverters receive the input waveforms at the inputs of the inverters and invert the input waveforms, producing a plurality of inverted waveforms at the outputs of the inverters. The system also includes NOR gates having inputs and outputs, wherein the NOR gates receive the plurality of inverted waveforms at the inputs of the NOR gates and pass through one of the inverted waveforms at the outputs of the NOR gates.

Abstract: Systems and methods for improving the timing alignment of 25% duty cycle non-overlapping waveforms are provided. A representative system includes a waveform synthesizer that generates a plurality of 25% duty cycle input waveforms and inverters that receive the input waveforms at the inputs of the inverters and invert the input waveforms, producing a plurality of inverted waveforms at the outputs of the inverters. The system also includes NOR gates that receive the plurality of inverted waveforms at the inputs of the NOR gates and pass through one of the inverted waveforms at the outputs of the NOR gates responsive to three inverted waveforms of the plurality of inverted waveforms being at logic “0”; and mixers having inputs that receive the pass-through waveform and a first radio frequency (RF) signal, wherein the mixers combine the pass-through waveform and the RF signal into an output signal.

Abstract: Systems and methods for improving the timing alignment of 25% duty cycle non-overlapping waveforms are provided. A representative system includes a waveform synthesizer that generates a plurality of 25% duty cycle input waveforms and inverters that receive the input waveforms at the inputs of the inverters and invert the input waveforms, producing a plurality of inverted waveforms at the outputs of the inverters. The system also includes NOR gates that receive the plurality of inverted waveforms at the inputs of the NOR gates and pass through one of the inverted waveforms at the outputs of the NOR gates responsive to three inverted waveforms of the plurality of inverted waveforms being at logic “0”; and mixers having inputs that receive the pass-through waveform and a first radio frequency (RF) signal, wherein the mixers combine the pass-through waveform and the RF signal into an output signal.

Abstract: A technique for calibrating a transceiver of a wireless communication device includes selectively coupling an output node of a transmitter of the transceiver to an input node of a receiver of the transceiver. A calibration signal is provided, from the output node of the transmitter, to the input node of the receiver. The calibration signal is down-converted, with the receiver, to provide a down-converted calibration signal. A discrete Fourier transform is performed on the down-converted calibration signal. Finally, one or more correction factors are determined based on an analysis of the discrete Fourier transform of the down-converted calibration signal. At least one of the correction factors is utilized to facilitate substantial cancellation of a direct current offset associated with the transceiver.

Abstract: A technique for calibrating a transceiver of a wireless communication device includes selectively coupling an output node of a transmitter of the transceiver to an input node of a receiver of the transceiver. A calibration signal is provided, from the output node of the transmitter, to the input node of the receiver. The calibration signal is down-converted, with the receiver, to provide a down-converted calibration signal. A discrete Fourier transform is performed on the down-converted calibration signal. Finally, one or more correction factors are determined based on an analysis of the discrete Fourier transform of the down-converted calibration signal. At least one of the correction factors is utilized to facilitate substantial cancellation of a direct current offset associated with the transceiver.

Abstract: An overtone crystal oscillator automatic calibration system including an overtone crystal oscillator with multiple programmable resistors and multiple amplifiers with supply voltage inputs and a calibration system. The calibration system adjusts the programmable resistors and the supply voltage inputs and detects oscillation of the overtone crystal oscillator. The calibration system adjusts the programmable resistors and the supply voltage input for each of multiple sequential steps to adjust the frequency bandwidth, such as from a higher bandwidth and lower gain to a lower bandwidth at higher gain. For example, each resistance level is tested for each of multiple supply voltage levels. The range of resistances and voltages is designed to ensure oscillation at a selected overtone frequency while avoiding oscillation at a fundamental frequency of the oscillator crystal. Oscillation may be detected by a counter which counts to a predetermined count value indicating successful oscillation.

Abstract: An overtone crystal oscillator including a crystal, multiple amplifiers and an RC network. The crystal has a fundamental resonance frequency and at least one overtone resonance frequency. The amplifiers are coupled in series between terminals of the crystal and the RC network is coupled to the amplifiers. The amplifiers and the RC network are collectively configured to suppress oscillation of the crystal at the fundamental resonance frequency and to enable oscillation at an overtone resonance frequency of the crystal. The amplifiers and the RC network may be configured to cause a phase shift between the fundamental resonance frequency and the overtone resonance frequency. The overtone resonance frequency may be any odd harmonic of the fundamental frequency, such as a third overtone of the crystal. The overtone crystal oscillator may be integrated with CMOS processes and does not require an inductor to suppress the fundamental mode of oscillation.

Abstract: An overtone crystal oscillator automatic calibration system including an overtone crystal oscillator with multiple programmable resistors and multiple amplifiers with supply voltage inputs and a calibration system. The calibration system adjusts the programmable resistors and the supply voltage inputs and detects oscillation of the overtone crystal oscillator. The calibration system adjusts the programmable resistors and the supply voltage input for each of multiple sequential steps to adjust the frequency bandwidth, such as from a higher bandwidth and lower gain to a lower bandwidth at higher gain. For example, each resistance level is tested for each of multiple supply voltage levels. The range of resistances and voltages is designed to ensure oscillation at a selected overtone frequency while avoiding oscillation at a fundamental frequency of the oscillator crystal. Oscillation may be detected by a counter which counts to a predetermined count value indicating successful oscillation.

Abstract: An overtone crystal oscillator including a crystal, multiple amplifiers and an RC network. The crystal has a fundamental resonance frequency and at least one overtone resonance frequency. The amplifiers are coupled in series between terminals of the crystal and the RC network is coupled to the amplifiers. The amplifiers and the RC network are collectively configured to suppress oscillation of the crystal at the fundamental resonance frequency and to enable oscillation at an overtone resonance frequency of the crystal. The amplifiers and the RC network may be configured to cause a phase shift between the fundamental resonance frequency and the overtone resonance frequency. The overtone resonance frequency may be any odd harmonic of the fundamental frequency, such as a third overtone of the crystal. The overtone crystal oscillator may be integrated with CMOS processes and does not require an inductor to suppress the fundamental mode of oscillation.

Abstract: A wideband level shift circuit (200) used with low voltage ECL or CML topologies. includes a sub-Vbe voltage reference (201) whose output voltage is offset some fraction of a diode voltage drop below a supply voltage, where the fraction is held at a constant value as the diode voltage varies with temperature. A comparator circuit (203) is attached to the reference voltage circuit (201) as well as to a current sourcing transistor and differential buffer circuit (205). The comparator circuit (203) maintains the DC potential at the output of a current sourcing transistor so that the common-mode DC level of the output signal from a differential buffer is shifted down by a fraction of a diode drop from the common-mode DC level of a wideband AC input signal. The shift circuit (200) offers the advantages of a fraction of a diode DC voltage drop with little loss of AC signal bandwidth for circuits operating from low supply voltages.

Abstract: A wideband level shift circuit (200) used with low voltage ECL or CML topologies includes a sub-Vbe voltage reference (201) whose output voltage is offset some fraction of a diode voltage drop below a supply voltage, where the fraction is held at a constant value as the diode voltage varies with temperature. A comparator circuit (203) is attached to the reference voltage circuit (201) as well as to a current sourcing transistor and differential buffer circuit (205). The comparator circuit (203) maintains the DC potential at the output of a current sourcing transistor so that the common-mode DC level of the output signal from a differential buffer is shifted down by a fraction of a diode drop from the common-mode DC level of a wideband AC input signal. The shift circuit (200) offers the advantages of a fraction of a diode DC voltage drop with little loss of AC signal bandwidth for circuits operating from low supply voltages.

Abstract: A three-dimensional inductor coil is fabricated on top of a semiconductor substrate. The fabrication process includes the steps of depositing a first photoresist layer (406), forming a trench therein, and filling the trench with electroplated metal (404). A second photoresist layer (408) is deposited, and first and second trenches (410) are formed therein and filled with electroplated metal (412). A third photoresist layer (416) is deposited and a trench (418) formed therein, and then filled with electroplated metal (420). The first, second, and third photoresist layers (406, 408, 416) are then removed to expose a multi-loop inductor coil (500, 550).

Abstract: An automatic gain control circuit (100) provides precision gain control for amplified signals. An offset generator (130) generates an offset signal (132) from an output signal (108) of a variable gain amplifier, shifted according to a target signal level, and another offset signal (134) according to a base signal (106). A pulse train generator (140) compares the offset signals (108, 106) and provides a pulse train signal (142) having a particular energy content. A feedback signal (172) based on the particular energy content of the pulse train signal (142) is used to adjust the gain of the variable amplifier (110).