Abstract: Vector magnitude approximating logic using logarithms of the vector's orthogonal components to select multiplier scaling constants and to minimize arithmetic-function and hardware complexity. The apparatus is particularly applicable to a high-throughput, pipelined, digital signal processing application such as radar. The vector magnitude is approximated by multiplying each component of a complex number representing the vector by selected scaling constants and then by summing the two resulting products. The scaling constants are selected by feeding each orthogonal component of the vector into one of two identical logic arrays which determine the base-2 logarithm of the absolute value of each component.

Abstract: A bus interconnects a plurality of elements to form a distributed signal processing system. When two or more elements attempt to use the bus simultaneously, a method of arbitration occurs whereby each element places its element arbitration code on assigned lines of the bus forming a composite complementary code. Arbitration apparatus in each element determines an element's priority relative to other elements based on said composite complementary code. The lower priority elements drop off the bus until only the highest priority is left whereupon it uses the bus to transmit its block of data.