Abstract: An integrated memory circuit includes a high-voltage switch which is connected between a programming voltage generator and an erasable programmable memory. In the preferred embodiment of the memory circuit, the switch includes a first transistor of the field-effect enhancement type which is connected between a high-voltage point and a control electrode of a second transistor, also being of the field-efffect enhancement type, which is connected between the high-voltage point and the control electrode of the first transistor. By driving the two control electrodes by means of mutually complementary clock signals, via a capacitance, the programming voltage is step-wise built up on the control electrodes of the cross-wise coupled transistors. The switch is less susceptible to crosstalk on the clock lines and is realized using fewer masking steps than the prior art switch.

Abstract: A semiconductor device having one or more first non-volatile memory transistors and a detector having a second non-volatile memory transistor with which a charge level written in the first transistor is safeguarded and corrected, if necessary, by a suitable, incorporated bias voltage between source zone and control electrode and/or a margin fixed by an incorporated difference in threshold voltage. A further non-volatile memory transistor may be present with which there is detected, during writing, erasing or rewritting, whether the desired charge level in the first transistor is reached and the charge transport is to be terminated.