Abstract: A processor system with micro-threading control by a hardware-accelerated kernel thread and the scheduling methods thereof are provided. The processor system comprises a plurality of processor cores and a mutex processing unit connected with the plurality of processor cores. Each processor core provides a kernel thread and a plurality of user threads for concurrent execution, and each processor core comprises a kernel trigger module configured to monitor a set of trigger conditions and generate a kernel triggering indicator to activate the kernel thread in the processor core. The mutex processing unit is configured to receive a plurality of mutex requests from each processor core, and broadcast a plurality of mutex responses to each processor core. Each of the plurality of mutex requests is configured to create a mutex response that affects an execution status of at least one user thread in the plurality of processor cores.

Abstract: A processor system with micro-threading control by a hardware-accelerated kernel thread and the scheduling methods thereof are provided. The processor system comprises at least one processor core and a mutex processing unit connected with the at least one processor core. Each processor core provides a kernel thread and a plurality of user threads for concurrent execution, and each processor core comprises a kernel trigger module configured to monitor a set of trigger conditions and generate a kernel triggering indicator to activate the kernel thread in the processor core. The mutex processing unit is configured to receive a plurality of mutex requests from each processor core, and broadcast a plurality of mutex responses to each processor core. Each of the plurality of mutex requests aims to create a mutex response that affect an execution status of at least one user thread in at least one of the processor cores.

Abstract: An electronic system that executes video streaming includes a video sender. The video sender converts video data into plural layers of bitstream packets with varied priorities for transmission. A bitstream packet with a lower layer of the plural layers of bitstream packets has a higher priority when being transmitted to a video receiver.

Abstract: A method minimizes audio and video streaming delays between a video source and a video sink. A receiver receives a netsync message from a transmitter that communicates with the video source to receive input video. The netsync message is generated by the transmitter in accordance with the input video and indicates a display pointer of the transmitter. In accordance with the netsync message, the receiver adaptively outputs a set of timing control signals that is transmitted to the video sink, thereby minimizing the latency between the vertical synchronization (VSYNC) of the transmitter and the VSYNC of the receiver.

Abstract: An electronic system that executes video streaming includes a video sender. The video sender converts video data into plural layers of bitstream packets with varied priorities for transmission. A bitstream packet with a lower layer of the plural layers of bitstream packets has a higher priority when being transmitted to a video receiver.

Abstract: An electronic system that executes video streaming includes a video sender. The video sender converts video data into plural layers of bitstream packets with varied priorities for transmission. A bitstream packet with a lower layer of the plural layers of bitstream packets has a higher priority when being transmitted to a video receiver.

Abstract: An electronic system that executes video streaming includes a video sender. The video sender converts video data into plural layers of bitstream packets with varied priorities for transmission. A bitstream packet with a lower layer of the plural layers of bitstream packets has a higher priority when being transmitted to a video receiver.

Abstract: A method minimizes audio and video streaming delays between a video source and a video sink. A receiver receives a netsync message from a transmitter that communicates with the video source to receive input video. The netsync message is generated by the transmitter in accordance with the input video and indicates a display pointer of the transmitter. In accordance with the netsync message, the receiver adaptively outputs a set of timing control signals that is transmitted to the video sink, thereby minimizing the latency between the vertical synchronization (VSYNC) of the transmitter and the VSYNC of the receiver.

Abstract: The claimed invention is an efficient and high-performance vector processor. Through minimizing the use of multiple banks of memory and/or multi-ported memory blocks to reduce implementation cost, vector memory 450 provides abundant memory bandwidth and enables sustained low-delay memory operations for a large number of SIMD (Single Instruction, Multiple Data) or vector operators simultaneously.

Abstract: A shared memory switch architecture provides per-flow queuing that achieves high memory bandwidth and makes efficient use of memory. The memory of the memory switch is dynamically allocated to each port based on real-time traffic conditions. The priority of the packets is represented by queuing elements having a priority level determined by a weighted fair queue algorithm and its variants. The priority arbitration of queuing elements is made according to a two level hierarchy to increase the speed of priority queue management and therefore the switching throughput.

Abstract: A content addressable memory is implemented as a memory with a L-level hierarchy. When accessing the memory, key data is compared at each level of the hierarchy to determine whether an exact match, a longest prefix match exists. The CAM may be implemented with a two level hierarchy and a memory configuration that stores keys in cyclical ascending or cyclical descending order. Each memory row may include row logic to create the first level hierarchical data directly from its row data. The row data itself comprises the second level hierarchical data. During the search process, the key data is compared to the first level hierarchical data which narrows the search to only particular memory rows for the exact match or longest prefix match operation. This architecture is fast, power efficient and makes efficient use of transistors.