Patents by Inventor Ronald D. Holifield

Ronald D. Holifield has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for detecting floating nodes within a simulated integrated circuit
    Patent number: 6285975
    Abstract: A method and apparatus for detecting floating transistor gates within a netlist model of an integrated circuit is disclosed. All transistor gates and input nodes coupled to the transistor gates are identified. These input nodes are then used to generate a resistor card. The resistor card is used in conjunction with the original netlist during simulation to couple two resistors to each input node. The first resistor is coupled between the input node and a high potential, and the second resistor is coupled between the input node and a lower potential. The resistors may be configured to have equal resistance values. The resistance values may be large enough to ensure that the current conducted through the resistors will be minimal in relation to the currents in the circuit when the input node is not floating. The resistance values may be small enough to overcome any leakage currents present in the circuit.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: September 4, 2001
    Assignee: Legarity, Inc.
    Inventors: Vijayakumaran V. Nair, Ronald D. Holifield
  • System and method for detecting floating nodes within a simulated integrated circuit
    Patent number: 6090149
    Abstract: A method and apparatus for detecting floating transistor gates within a netlist model of an integrated circuit is disclosed. All transistor gates and input nodes coupled to the transistor gates are identified. These input nodes are then used to generate a resistor card. The resistor card is used in conjunction with the original netlist during simulation to couple two resistors to each input node. The first resistor is coupled between the input node and a high potential, and the second resistor is coupled between the input node and a lower potential. The resistors may be configured to have equal resistance values. The resistance values may be large enough to ensure that the current conducted through the resistors will be minimal in relation to the currents in the circuit when the input node is not floating. The resistance values may be small enough to overcome any leakage currents present in the circuit.
    Type: Grant
    Filed: February 19, 1998
    Date of Patent: July 18, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vijayakumaran V. Nair, Ronald D. Holifield