Abstract: A system and method communicate information from a single-threaded application over multiple I/O busses to a computing subsystem for processing. In accordance with one embodiment, a method is provided that partitions state-sequenced information for communication to a computer subsystem, communicates the partitioned information to the subsystem over a plurality of input/output busses, and separately processes the information received over each of the plurality of input/output busses, without first se-sequencing the information.

Abstract: A multi-function unit for occlusion testing primitives being processed in a graphics system and for updating a Z pyramid data structure used for occlusion testing. The Z pyramid data structure is updated on the fly, i.e., as primitives are being occlusion tested. The apparatus comprises multi-function unit is configured to create the Z pyramid data structure and to perform occlusion testing. The Z pyramid data structure comprises a plurality of levels, each of which comprises a plurality of regions. Each region comprises a plurality of subregions, each of which corresponds to a single Z value. Each region corresponds to a plurality of Z values and has a maximum region Z value, which corresponds to the largest Z value of the region. The multi-function unit compares the minimum Z value of each primitive with the maximum Z value of a region associated with the tested primitive to determine whether or not the tested primitive is fully occluded.

Abstract: In one embodiment, selecting a screen region on a screen of a monitor of a computer graphics display system to activate in rendering a straight line segment. Steps of aligning a rectangular grid to screen region boundaries, wherein the screen includes a screen space divided into at least one screen region, locating a first and second endpoints of the straight line segment on the screen space, defining a rectangular bounding box in the screen space having vertices at the first and second endpoints, identifying each screen region that at least partially overlaps the bounding box, and selecting each identified screen region through which the straight line segment passes to activate for rendering the straight line segment on the screen are disclosed.

Abstract: Systems and methods are provided for performing a BLT (BLock Transfer). In accordance with one embodiment, a method uses a texture-mapping subsystem to perform the BLT by configuring the texture-mapping subsystem with coordinate values corresponding to a block of pixels to be transferred. In accordance with another embodiment, an apparatus comprises logic for defining a texture map from a source segment of memory corresponding to a frame buffer, logic for configuring a texture-mapping subsystem with coordinate values corresponding to a first block of pixels on a display, logic for using a texture-mapping subsystem to apply the texture map defined by the configured coordinate values to a destination segment of memory corresponding to a second block of pixels on the graphic display, wherein the application of the texture map effects a BLT of the data from the first block of pixels to the second block of pixels.

Abstract: In one embodiment, selecting a screen region on a screen of a monitor of a computer graphics display system to activate in rendering a straight line segment. Steps of aligning a rectangular grid to screen region boundaries, wherein the screen includes a screen space divided into at least one screen region, locating a first and second endpoints of the straight line segment on the screen space, defining a rectangular bounding box in the screen space having vertices at the first and second endpoints, identifying each screen region that at least partially overlaps the bounding box, and selecting each identified screen region through which the straight line segment passes to activate for rendering the straight line segment on the screen are disclosed.

Abstract: In one embodiment, selecting a screen region on a screen of a monitor of a computer graphics display system to activate in rendering a straight line segment. Steps of aligning a rectangular grid to screen region boundaries, wherein the screen includes a screen space divided into at least one screen region, locating a first and second endpoints of the straight line segment on the screen space, defining a rectangular bounding box in the screen space having vertices at the first and second endpoints, identifying each screen region that at least partially overlaps the bounding box, and selecting each identified screen region through which the straight line segment passes to activate for rendering the straight line segment on the screen are disclosed.

Abstract: Systems and methods are provided for performing a BLT (BLock Transfer). In accordance with one embodiment, a method uses a texture-mapping subsystem to perform the BLT by configuring the texture-mapping subsystem with coordinate values corresponding to a block of pixels to be transferred. In accordance with another embodiment, an apparatus comprises logic for defining a texture map from a source segment of memory corresponding to a frame buffer, logic for configuring a texture-mapping subsystem with coordinate values corresponding to a first block of pixels on a display, logic for using a texture-mapping subsystem to apply the texture map defined by the configured coordinate values to a destination segment of memory corresponding to a second block of pixels on the graphic display, wherein the application of the texture map effects a BLT of the data from the first block of pixels to the second block of pixels.

Abstract: An apparatus and method of selectively over-sampling image data, anti-aliasing of polygons that produces quality images comparing favorably to full over-sampling techniques while requiring less computation than full over-sampling techniques. Using a hierarchical tiler to perform edge calculations for any given polygon, and then selectively over-sampling pixels along the edge, image quality may be greatly improved through anti-aliasing the polygon edges, with a small increase in computation time or hardware.

Abstract: In one embodiment, selecting a screen region on a screen of a monitor of a computer graphics display system to activate in rendering a straight line segment. Steps of aligning a rectangular grid to screen region boundaries, wherein the screen includes a screen space divided into at least one screen region, locating a first and second endpoints of the straight line segment on the screen space, defining a rectangular bounding box in the screen space having vertices at the first and second endpoints, identifying each screen region that at least partially overlaps the bounding box, and selecting each identified screen region through which the straight line segment passes to activate for rendering the straight line segment on the screen are disclosed.

Abstract: An apparatus and method of selectively over-sampling image data, anti-aliasing of polygons that produces quality images comparing favorably to full over-sampling techniques while requiring less computation than full over-sampling techniques. Using a hierarchical tiler to perform edge calculations for any given polygon, and then selectively over-sampling pixels along the edge, image quality may be greatly improved through anti-aliasing the polygon edges, with a small increase in computation time or hardware.

Abstract: A method and apparatus for performing scan conversion in a computer graphics display system to determine pixel locations in screen space which correspond to a primitive being scan converted. The apparatus of the present invention comprises logic configured to convert a primitive into pixel locations in screen space. The logic, which is referred to hereinafter as the hierarchical tiler, subdivides the screen space into a plurality of regions, each of which comprises a plurality of pixel locations in screen space. The hierarchical tiler then determines whether a particular one of the regions is entirely outside of the primitive, entirely inside of the primitive, or partially inside of the primitive. If the hierarchical tiler determines that a particular region is entirely inside of the primitive, it converts the particular region into pixel locations in screen space.

Abstract: A method and apparatus is provided for performing Z depth comparison tests in a computer graphics display system. The minimum and maximum Z values are calculated for each region of Z values stored in a Z buffer memory device. When a Z value to be tested is received, the Z value is tested against the maximum Z value to determine whether the primitive is occluded. The maximum Z value corresponds to the largest Z value of a region of Z values. The minimum Z value corresponds to the smallest Z value of all of the Z values of the region. If a determination is made that the primitive is not occluded, the received Z value is tested against the minimum Z value. If a determination is made that the received Z value is less than the minimum Z value, the received Z value is retained and is ultimately stored in the Z buffer memory element. The minimum and maximum Z values are updated using the Z values which are contained in the Z buffer memory element.

Abstract: A method and apparatus is provided for interleaving frame buffer controllers in two dimensions. Each frame buffer controller includes an edge stepper, a subspan stepper and a span stepper. The subspan stepper separates each span line into a plurality of parts. Each frame buffer controller provides pixel data for certain parts of the span line. The parts are defined by a start value, a stop value and a starting color value.

Abstract: Several graphics processing elements are interconnected in a ring using a plurality of individual busses. Each bus interconnects a pair of the graphics processing elements and includes a like group of signal lines for transferring graphics command signals and information signals between graphics processing elements in the ring.

Abstract: An interface circuit included in a ring interconnected group of processing elements includes a backup FIFO to temporarily store information received by the interface circuit when it receives an indication that it temporarily should not forward information to the next processing element in the ring. The interface circuit can receive such an indication, for example, when it receives a signal from the downstream processing element in the ring indicating that the downstream circuit is unable to receive information, or when it receives an information packet requesting a read from the core of the processing element. When the interface circuit receives such an indication, it de-asserts an outgoing ready signal to the upstream processing element in the ring, which should cause the upstream processing element to stop sending information.

Abstract: An interface circuit receives both priority and non-priority information non-concurrently on a shared input bus during a first clock cycle and transmits the information received during the first clock cycle non-concurrently to a shared output bus during a second clock cycle following the first clock cycle. The received information includes status data identifying it as being either priority or non-priority information. All received information is provided to an external circuit via either a priority information path or a non-priority information path, depending on whether the status data included with the information identifies it as being priority or non-priority information. When the interface circuit is unable to transmit information, received information is backed up into either a priority or a non-priority information path, depending on whether the status data included with the information identifies it as being priority or non-priority information.

Abstract: A computer graphics system utilizes caching of pixel Z values to improve rendering performance. Apparatus for updating the Z values corresponding to pixels of a computer graphics display includes a memory for storing current Z values representing depths at corresponding pixel locations, a Z cache for storing a subset of the current Z values which are stored in the memory, and a comparator for comparing a new Z value with a corresponding current Z value and indicating a pass when the new Z value satisfies a predetermined criteria. The current Z value is read from the Z cache when the current Z value is stored in the Z cache and is read from the memory when the current Z value is not stored in the Z cache. The new Z value is written into the Z cache when the comparator indicates a pass. Each cache entry preferably includes a tile of current Z values corresponding to pixels having a predefined relationship. Different tile configurations may be selected for optimum rendering performance.

Abstract: Graphics window systems which utilize graphics pipelines and graphics pipeline bypass buses. Hardware solutions for window relative rendering of graphics primitives, block moving of graphics primitives, transfer of large data blocks, and elimination of pipeline flushing are disclosed. The hardware implementations provided in accordance with the invention are interfaced along the pipeline bypass bus, thereby eliminating gross overhead processor time for the graphics pipeline and reducing pipeline latency. Methods and apparatus provided in accordance with the invention exhibit significant pipeline efficiency and reductions in time to render graphics primitives to the screen system.

Abstract: Graphics window systems which utilize graphics pipelines and graphics pipeline bypass buses. Hardware solutions for window relative rendering of graphics primitives, block moving of graphics primitives, transfer of large data blocks, and elimination of pipeline flushing are disclosed. The hardware implementations provided in accordance with the invention are interfaced along the pipeline bypass bus, thereby eliminating gross overhead processor time for the graphics pipeline and reducing pipeline latency. Methods and apparatus provided in accordance with the invention exhibit significant pipeline efficiency and reductions in time to render graphics primitives to the screen system.

Abstract: Graphics window systems which utilize graphics pipelines and graphics pipeline bypass buses. Hardware solutions for window relative rendering of graphics primitives, block moving of graphics primitives, transfer of large data blocks, and elimination of pipeline flushing are disclosed. The hardware implementations provided in accordance with the invention are interfaced along the pipeline bypass bus, thereby eliminating gross overhead processor time for the graphics pipeline and reducing pipeline latency. Methods and apparatus provided in accordance with the invention exhibit significant pipeline efficiency and reductions in time to render graphics primitives to the screen system.