Abstract: Systems and methods are provided for testing a threshold energy required to cause a latchup on an electronic component. An exemplary method includes applying a series of laser pulses to a testing object with a pulsed laser unit. The testing object is connected to a testing circuit which can measure the energy of each of the series of laser pulses, and detect whether a pulse of the series of laser pulses resulted in a latchup on the testing object. Upon detecting the pulse, the method provides for logging the energy of the pulse using a recording unit and logging the latchup status of the test device. If a latchup is detected, the testing circuit automatically mitigates the latchup event.

Abstract: Systems and methods are provided for testing a threshold energy required to cause a latchup on an electronic component. An exemplary method includes applying a series of laser pulses to a testing object with a pulsed laser unit. The testing object is connected to a testing circuit which can measure the energy of each of the series of laser pulses, and detect whether a pulse of the series of laser pulses resulted in a latchup on the testing object. Upon detecting the pulse, the method provides for logging the energy of the pulse using a recording unit and logging the latchup status of the test device. If a latchup is detected, the testing circuit automatically mitigates the latchup event.

Abstract: Systems and methods are provided for testing a threshold energy required to cause a latchup on an electronic component. An exemplary method includes applying a series of laser pulses to a testing object with a pulsed laser unit. The testing object is connected to a testing circuit which can measure the energy of each of the series of laser pulses, and detect whether a pulse of the series of laser pulses resulted in a latchup on the testing object. Upon detecting the pulse, the method provides for logging the energy of the pulse using a recording unit and logging the latchup status of the test device. If a latchup is detected, the testing circuit automatically mitigates the latchup event.

Abstract: Systems and methods are provided for testing a threshold energy required to cause a latchup on an electronic component. An exemplary method includes applying a series of laser pulses to a testing object with a pulsed laser unit. The testing object is connected to a testing circuit which can measure the energy of each of the series of laser pulses, and detect whether a pulse of the series of laser pulses resulted in a latchup on the testing object. Upon detecting the pulse, the method provides for logging the energy of the pulse using a recording unit and logging the latchup status of the test device. If a latchup is detected, the testing circuit automatically mitigates the latchup event.

Abstract: A monocrystalline monolith contains a 3-D array of interconnected lattice-matched devices (which may be of one kind exclusively, or that kind in combination with one or more other kinds) performing digital, analog, image-processing, or neural-network functions, singly or in combination. Localized inclusions of lattice-matched metal and (or) insulator can exist in the monolith, but monolith-wide layers of insulator are avoided. The devices may be self-isolated, junction-isolated, or insulator-isolated, and may include but not be limited to MOSFETs, BJTs, JFETs, MFETs, CCDs, resistors, and capacitors. The monolith is fabricated in a single apparatus using a process such as MBE or sputter epitaxy executed in a continuous or quasicontinuous manner under automatic control, and supplanting hundreds of discrete steps with handling and storage steps interpolated.

Abstract: A method is described for growing a single crystal having three-dimensional (3-D) doping patterns created within it during growth while maintaining a plane growth surface, creating junction-isolated devices and interconnections, forming a 3-D integrated circuit (IC). The crystal is grown as a large number of lightly-doped layers in a single-pumpdown procedure using sputter epitaxy, which offers growth rates for good-quality silicon of at least 0.1 micrometer per minute. The process experiences a stable environment with temperature remaining around 400 C and pressure near 1 millitorr, and the process is "quasicontinuous" in that once each layer is in place, its surface will experience a short series of further steps that create a 2-D doping pattern extending through the layer. It is the merging of many such successive 2-D patterns that creates the desired 3-D doping pattern within the finished silicon crystal.

Abstract: A system evaluates occurrences of low level electrostatic discharge events in a manufacturing or processing environment or the like by encapsulating each of a plurality of a MOSFETs in a corresponding package having conductive first and second groups of leads coupled to the gate and source and/or drain electrodes of the MOSFET, respectively. The encapsulated MOSFET then is moved through the environment, wherein an electrostatic discharge causes current to flow into the first external electrode, stressing the gate oxide of the MOSFET and producing a permanent low resistance condition therein. The encapsulated MOSFET then is removed from the environment and tested by measuring an electrical parameter indicative of the low resistance condition between the first and second electrodes of the MOSFET. A statistical analysis then is performed on the data obtained by testing all of the MOSFETs to determine how to reduce or avoid ESD in the environment.

Abstract: A system evaluates occurrences of low level electrostatic discharge events in a manufacturing or processing environment or the like by encapsulating each of a plurality of a MOSFETs in a corresponding package having conductive first and second groups of leads coupled to the gate and source and/or drain electrodes of the MOSFET, respectively. The encapsulated MOSFET then is moved through the environment, wherein an electrostatic discharge causes current to flow into the first external electrode, stressing the gate oxide of the MOSFET and producing a permanent low resistance condition therein. The encapsulated MOSFET then is removed from the environment and tested by measuring an electrical parameter indicative of the low resistance condition between the first and second electrodes of the MOSFET. A statistical analysis then is performed on the data obtained by testing all of the MOSFETs to determine how to reduce or avoid ESD in the environment.

Abstract: A monocrystalline monolith contains a 3-D array of interconnected lattice-matched devices (which may be of one kind exclusively, or that kind in combination with one or more other kinds) performing digital, analog, image-processing, or neural-network functions, singly or in combination. Localized inclusions of lattice-matched metal and (or) insulator can exist in the monolith, but monolith-wide layers of insulator are avoided. The devices may be self-isolated, junction-isolated, or insulator-isolated, and may include but not be limited to MOSFETs, BJTs, JFETs, MFETs, CCDs, resistors, and capacitors. The monolith is fabricated in a single apparatus using a process such as MBE or sputter epitaxy executed in a continuous or quasicontinuous manner under automatic control, and supplanting hundreds of discrete steps with handling and storage steps interpolated.

Abstract: A single-crystal monolith containing a 3-D doping pattern forming varied devices and circuits that are junction-isolated. The semiconductor monolith includes interconnecting signal paths and power buses, also junction-isolated, usually with N+ regions within P matrix regions, and tunnel junctions, N+ - P+ junctions, as ohmic contacts from N-type to P-type regions. An isolating box incorporates an orthogonal isolator. The 3-D structure places layers of critical profile normal to the growth axis. The orthogonal isolator can include floating elements. The 3-D semiconductor monolith can be manufactured through continuous or quasicontinuous processing in a closed system, such as through MBE or sputter epitaxy. Also, a thin layer of silicide can be provided as an ohmic contact and/or a thick layer of silicide can be provided as a conductor thereby providing monocrystalline 3-D devices or integrated circuits. Finally, an insulator can be provided about an entire device for isolation.

Abstract: A single-crystal monolith containing a 3-D doping pattern forming varied devices and circuits that are junction-isolated. The semiconductor monolith includes interconnecting signal paths and power buses, also junction-isolated, usually with N+ regions within P matrix regions, and tunnel junctions, N+-P+ junctions, as ohmic contacts from N-type to P-type regions. An isolating box incorporates an orthogonal isolator. The 3-D structure places layers of critical profile normal to the growth axis. The orthogonal isolator can include floating elements. The 3-D semiconductor monolith can be manufactured through continuous or quasicontinuous processing in a closed system, such as through MBE or sputter epitaxy.