Abstract: A protective assembly that is adapted to provide temperature isolation for an electronic device is disclosed. The assembly includes a housing having a cavity with a top surface and at least one side surface. The housing is configured to accept an electronic device having a top and a bottom in the cavity with the top of the electronic device proximate to the top surface of the cavity. The housing is further configured to maintain a vacuum within the cavity. The assembly includes at least one support disposed within the cavity. The at least one support is configured to contact the housing only at a first point proximate to the top surface of the cavity and contact the electronic device only at a second point that is proximate to the bottom of the electronic device.

Abstract: A method, system, computer program product, and expansion card capable of: defining an initial source address within a source memory device. An initial data read operation is performed to retrieve a first X-byte data portion from the source memory device. The initial data read operation begins at the initial source address. The initial source address is incremented by Y bytes to define a secondary source address within the source memory device, such that Y is greater than X.

Abstract: Techniques are described herein that may utilize capabilities of a data mover in order to determine an integrity validation value or perform an integrity checking operation. The integrity validation value determination and integrity checking operations may be controlled by descriptors or instructions. In some implementations, integrity validation value determination and the integrity checking operations may include determination of a cyclical redundancy checking (CRC) value.

Abstract: A method and an apparatus to prevent over subscription and thrashing of translation lookaside buffer (TLB) entries in I/O virtualization hardware have been presented. In one embodiment, the method includes performing address translation in a direct memory access (DMA) remap engine within an input/output (I/O) hub in response to I/O requests from a root port using a guest physical address (GPA) queue to temporarily hold address translations requests to service the I/O requests and a TLB. The method may further include managing allocation of entries in the TLB to the address translation requests using an allocation window to avoid over-subscription of the entries and managing de-allocation of the entries using a de-allocation window to avoid thrashing of the entries. Other embodiments have been claimed and described.

Abstract: A method and an apparatus to track address translation in I/O virtualization have been presented. In one embodiment, the method includes initiating a page walk if none of a plurality of entries in a translation lookaside buffer (TLB) in a direct memory access (DMA) remap engine matches a guest physical address of an incoming address translation request. The method further includes performing the page walk in parallel with one or more ongoing page walks and tracking progress of the page walk using one or more of a plurality of flags and state information pertaining to intermediate states of the page walk stored in the TLB. Other embodiments have been claimed and described.

Abstract: A method, system, computer program product, and expansion card capable of: defining an initial source address within a source memory device. An initial data read operation is performed to retrieve a first X-byte data portion from the source memory device. The initial data read operation begins at the initial source address. The initial source address is incremented by Y bytes to define a secondary source address within the source memory device, such that Y is greater than X.

Abstract: The present invention is directed to buffer arrangements (e.g., via concatenation) to support differential link distances at full bandwidth.