Abstract: According to embodiments of the present invention are systems and methods for using scan chains for the creation of unique physically uncloneable function (PUF). In particular, the present invention uses existing circuitry on an integrated circuit and the internal-scan or boundary-scan register to create a unique identifier for each integrated chip. The unique nature of the scan chains results from the inherent variability of the manufacturing process.

Abstract: According to embodiments of the present invention are systems and methods for using scan chains for the creation of unique physically uncloneable function (PUF). In particular, the present invention uses existing circuitry on an integrated circuit and the internal-scan or boundary-scan register to create a unique identifier for each integrated chip. The unique nature of the scan chains results from the inherent variability of the manufacturing process.

Abstract: A method and apparatus for identifying suspect layout features from a plurality of layout features of an integrated circuit (IC) layout. A plurality of snippet images is generated, each of which depicts at least a portion of a suspect layout feature which is different from suspect layout features depicted in others of the plurality of snippet images. The suspect layout features are determined based on the diagnosis of a plurality of defective ICs manufactured in accordance with the IC layout. A plurality of clusters is generated, and each of the clusters contains a group of the plurality of snippet images based on similarities between the snippet images.

Abstract: A method and apparatus for identifying suspect layout features from a plurality of layout features of an integrated circuit (IC) layout. A plurality of snippet images is generated, each of which depicts at least a portion of a suspect layout feature which is different from suspect layout features depicted in others of the plurality of snippet images. The suspect layout features are determined based on the diagnosis of a plurality of defective ICs manufactured in accordance with the IC layout. A plurality of clusters is generated, and each of the clusters contains a group of the plurality of snippet images based on similarities between the snippet images.

Abstract: A method and apparatus are disclosed in which defect behavior in an integrated circuit is discovered and modeled rather than assuming defect behavior in the form of a fault. A plurality of tests are performed on an integrated circuit to produce passing and failing responses. The failing responses are examined in conjunction with circuit description data to identify fault locations. For at least certain of the fault locations, the logic-level conditions at neighboring locations which describe the behavior of a failing response are identified. Those logic level conditions are combined into a macrofault for that location. The macrofault is then validated and can be then used to identify more tests for further refining the diagnosis. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: The present disclosure is directed to an apparatus and method for producing and comparing signals from various points in a MEMS device. By producing signals which should be of substantial identical characteristics, deviations from the situation where the signals are of identical characteristics can be used to identify various types of asymmetry which are otherwise difficult to detect. In one embodiment, the MEMS device is comprised of a plurality of fixed beams arranged symmetrically and a plurality of movable beams arranged symmetrically. A first sensor is formed by certain of the fixed and movable beams while a second sensor, electrically isolated from said first sensor, is formed by at least certain other of the fixed and movable beams. The first and second sensors are located within the MEMS device so as to produce signals of substantially identical characteristics. A circuit is responsive to the first and second sensors for comparing the signals produced by the first and second sensors.

Abstract: A fault in an integrated circuit device can be characterized using fault tuples. In particular, an integrated circuit device can include primary inputs, primary outputs, and a plurality of signal lines and circuits interconnecting the primary inputs and outputs. A fault tuple is defined to include an identification of a signal line, a signal line value, and a clock cycle constraint for the signal line. A fault tuple is satisfied by providing a test sequence comprising one or more test patterns such that the signal line is controlled to the signal line value during a clock cycle of the test sequence defined by the clock cycle constraint responsive to application of the test sequence to the primary inputs. Fault tuples can be used to generate and simulate test sequences.

Abstract: A fault in an integrated circuit device can be characterized using fault tuples. In particular, an integrated circuit device can include primary inputs, primary outputs, and a plurality of signal lines and circuits interconnecting the primary inputs and outputs. A fault tuple is defined to include an identification of a signal line, a signal line value, and a clock cycle constraint for the signal line. A fault tuple is satisfied by providing a test sequence comprising one or more test patterns such that the signal line is controlled to the signal line value during a clock cycle of the test sequence defined by the clock cycle constraint responsive to application of the test sequence to the primary inputs. Fault tuples can be used to generate and simulate test sequences.