Patents by Inventor Ronald E. Freking
Ronald E. Freking has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9292460Abstract: Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration.Type: GrantFiled: February 25, 2013Date of Patent: March 22, 2016Assignee: International Business Machines CorporationInventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink
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Patent number: 9292462Abstract: Techniques for broadcasting a command in a distributed switch, at a first switch module within the distributed switch. Embodiments receive a request to reset a PCIe link for a first host device, the first host device connected to a plurality of downstream PCIe devices through the distributed switch. A routing table specifying a plurality of downstream switch modules, connected to the first switch modules by one or more ports of the first switch module, is identified. Embodiments suspend PCIe traffic for the first host device on the one or more ports of the first switch module. Broadcast messages are transmitted to the plurality of downstream switch modules, specifying a first reset operation. Upon receiving an acknowledgement message from each of the plurality of downstream switch modules specified in the routing table, embodiments resume PCIe traffic for the first host device on the one or more ports.Type: GrantFiled: May 22, 2013Date of Patent: March 22, 2016Assignee: International Business Machines CorporationInventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink
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Patent number: 9122604Abstract: Method for performing an operation to maintain data integrity in a parallel computing system, the operation comprising providing a lookup table specifying a plurality of predefined destinations for data packets, receiving a first data packet comprising a destination address specifying a first destination, wherein the first data packet has an error of a first type, identifying, from the lookup table, an entry specifying a second destination for data packets having errors of the first type, and sending the first data packet to the second destination.Type: GrantFiled: February 25, 2013Date of Patent: September 1, 2015Assignee: International Business Machines CorporationInventors: Ronald E. Freking, Elizabeth A. McGlone, Nicholas V. Tram, Curtis C. Wollbrink
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Patent number: 9087162Abstract: The standard hot-plug controller (SHPC) specification may be used to generate PCI messages in a distributed switch to disconnect and/or connect virtual hierarchies of an endpoint from hosts that are connected based on multi-root input/output virtualization (MR-IOV). A management controller may instruct a SHPC to generate a PCI packet that specifies a particular virtual hierarchy to disconnect from a particular host. An upstream port connected to the host and the SHPC receives the PCI packet and uses a header that identifies the virtual endpoint in the packet to index into a routing table to identify a downstream port in the distributed switch that is connected to the endpoint. Once the PCI packet traverses the switch and arrives at the downstream port, the downstream port changes routing logic which logically disconnects the host from the specified virtual hierarchy.Type: GrantFiled: February 26, 2013Date of Patent: July 21, 2015Assignee: International Business Machines CorporationInventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink
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Patent number: 9043526Abstract: Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration.Type: GrantFiled: June 20, 2012Date of Patent: May 26, 2015Assignee: International Business Machines CorporationInventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink
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Patent number: 8949499Abstract: The standard hot-plug controller (SHPC) specification may be used to generate PCI messages in a distributed switch to disconnect and/or connect virtual hierarchies of an endpoint from hosts that are connected based on multi-root input/output virtualization (MR-IOV). A management controller may instruct a SHPC to generate a PCI packet that specifies a particular virtual hierarchy to disconnect from a particular host. An upstream port connected to the host and the SHPC receives the PCI packet and uses a header that identifies the virtual endpoint in the packet to index into a routing table to identify a downstream port in the distributed switch that is connected to the endpoint. Once the PCI packet traverses the switch and arrives at the downstream port, the downstream port changes routing logic which logically disconnects the host from the specified virtual hierarchy.Type: GrantFiled: June 20, 2012Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink
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Publication number: 20140351484Abstract: Techniques for broadcasting a command in a distributed switch, at a first switch module within the distributed switch. Embodiments receive a request to reset a PCIe link for a first host device, the first host device connected to a plurality of downstream PCIe devices through the distributed switch. A routing table specifying a plurality of downstream switch modules, connected to the first switch modules by one or more ports of the first switch module, is identified. Embodiments suspend PCIe traffic for the first host device on the one or more ports of the first switch module. Broadcast messages are transmitted to the plurality of downstream switch modules, specifying a first reset operation. Upon receiving an acknowledgement message from each of the plurality of downstream switch modules specified in the routing table, embodiments resume PCIe traffic for the first host device on the one or more ports.Type: ApplicationFiled: May 22, 2013Publication date: November 27, 2014Applicant: International Business Machines CorporationInventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink
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Patent number: 8898359Abstract: Method, circuit, and system for performing an operation for regulating bandwidth, the operation comprising receiving at a memory, debug data packets and functional data packets for transmittal on a shared bus. The operation then transmits, via the shared bus, the functional data packets and one or more of the debug data packets according to a predefined ratio of debug data packets to functional data packets. The operation then drops one or more of the received debug data packets at the memory, and maintains a count of the one or more dropped debug data packets. The operation then updates the predefined ratio based on the count, and uses the updated predefined ratio to transmit the functional data packets and one or more of the debug data packets.Type: GrantFiled: February 26, 2013Date of Patent: November 25, 2014Assignee: International Business Machines CorporationInventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink
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Patent number: 8793539Abstract: Method, computer program product, and system for performing an operation to maintain data integrity in a parallel computing system, the operation comprising providing a lookup table specifying a plurality of predefined destinations for data packets, receiving a first data packet comprising a destination address specifying a first destination, wherein the first data packet has an error of a first type, identifying, from the lookup table, an entry specifying a second destination for data packets having errors of the first type, and sending the first data packet to the second destination.Type: GrantFiled: June 13, 2012Date of Patent: July 29, 2014Assignee: International Business Machines CorporationInventors: Ronald E. Freking, Elizabeth A. McGlone, Nicholas V. Tram, Curtis C. Wollbrink
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Patent number: 8706938Abstract: Method, circuit, and system for performing an operation for regulating bandwidth, the operation comprising receiving at a memory, debug data packets and functional data packets for transmittal on a shared bus. The operation then transmits, via the shared bus, the functional data packets and one or more of the debug data packets according to a predefined ratio of debug data packets to functional data packets. The operation then drops one or more of the received debug data packets at the memory, and maintains a count of the one or more dropped debug data packets. The operation then updates the predefined ratio based on the count, and uses the updated predefined ratio to transmit the functional data packets and one or more of the debug data packets.Type: GrantFiled: June 20, 2012Date of Patent: April 22, 2014Assignee: International Business Machines CorporationInventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink
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Publication number: 20130346665Abstract: Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration.Type: ApplicationFiled: June 20, 2012Publication date: December 26, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink
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Publication number: 20130346662Abstract: The standard hot-plug controller (SHPC) specification may be used to generate PCI messages in a distributed switch to disconnect and/or connect virtual hierarchies of an endpoint from hosts that are connected based on multi-root input/output virtualization (MR-IOV). A management controller may instruct a SHPC to generate a PCI packet that specifies a particular virtual hierarchy to disconnect from a particular host. An upstream port connected to the host and the SHPC receives the PCI packet and uses a header that identifies the virtual endpoint in the packet to index into a routing table to identify a downstream port in the distributed switch that is connected to the endpoint. Once the PCI packet traverses the switch and arrives at the downstream port, the downstream port changes routing logic which logically disconnects the host from the specified virtual hierarchy.Type: ApplicationFiled: February 26, 2013Publication date: December 26, 2013Applicant: International Business Machines CorporationInventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink
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Publication number: 20130346801Abstract: Method, circuit, and system for performing an operation for regulating bandwidth, the operation comprising receiving at a memory, debug data packets and functional data packets for transmittal on a shared bus. The operation then transmits, via the shared bus, the functional data packets and one or more of the debug data packets according to a predefined ratio of debug data packets to functional data packets. The operation then drops one or more of the received debug data packets at the memory, and maintains a count of the one or more dropped debug data packets. The operation then updates the predefined ratio based on the count, and uses the updated predefined ratio to transmit the functional data packets and one or more of the debug data packets.Type: ApplicationFiled: June 20, 2012Publication date: December 26, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink
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Publication number: 20130346653Abstract: Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration.Type: ApplicationFiled: February 25, 2013Publication date: December 26, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink
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Publication number: 20130346802Abstract: Method, circuit, and system for performing an operation for regulating bandwidth, the operation comprising receiving at a memory, debug data packets and functional data packets for transmittal on a shared bus. The operation then transmits, via the shared bus, the functional data packets and one or more of the debug data packets according to a predefined ratio of debug data packets to functional data packets. The operation then drops one or more of the received debug data packets at the memory, and maintains a count of the one or more dropped debug data packets. The operation then updates the predefined ratio based on the count, and uses the updated predefined ratio to transmit the functional data packets and one or more of the debug data packets.Type: ApplicationFiled: February 26, 2013Publication date: December 26, 2013Applicant: International Business Machines CorporationInventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink
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Publication number: 20130339826Abstract: Method, computer program product, and system for performing an operation to maintain data integrity in a parallel computing system, the operation comprising providing a lookup table specifying a plurality of predefined destinations for data packets, receiving a first data packet comprising a destination address specifying a first destination, wherein the first data packet has an error of a first type, identifying, from the lookup table, an entry specifying a second destination for data packets having errors of the first type, and sending the first data packet to the second destination to avoid corrupting the first destination.Type: ApplicationFiled: June 13, 2012Publication date: December 19, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ronald E. Freking, Elizabeth A. McGlone, Nicholas V. Tram, Curtis C. Wollbrink
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Publication number: 20130339825Abstract: Method for performing an operation to maintain data integrity in a parallel computing system, the operation comprising providing a lookup table specifying a plurality of predefined destinations for data packets, receiving a first data packet comprising a destination address specifying a first destination, wherein the first data packet has an error of a first type, identifying, from the lookup table, an entry specifying a second destination for data packets having errors of the first type, and sending the first data packet to the second destination to avoid corrupting the first destination.Type: ApplicationFiled: February 25, 2013Publication date: December 19, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ronald E. Freking, Elizabeth A. McGlone, Nicholas V. Tram, Curtis C. Wollbrink
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Patent number: 8397100Abstract: Systems and methods to manage memory refreshes at a memory controller are disclosed. A method includes determining, at a memory controller device, that a number of transmission errors between a memory controller port and a memory redrive device exceeds an error threshold. The method may include initiating a first link retraining process between the memory controller port and the memory redrive device. The method may further include placing one or more dynamic random access memory modules associated with the memory redrive device in a self-refresh mode. The method may also include removing the one or more dynamic random access memory modules from the self-refresh mode after the link retraining process has completed. The method may further include enabling overlapping refreshes of the one or more dynamic random access memory modules.Type: GrantFiled: March 15, 2010Date of Patent: March 12, 2013Assignee: International Business Machines CorporationInventors: H. Lee Blackmon, Ronald E. Freking, Ryan S. Haraden, Joseph A. Kirscht, Elizabeth A. McGlone
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Publication number: 20120311221Abstract: The standard hot-plug controller (SHPC) specification may be used to generate PCI messages in a distributed switch to disconnect and/or connect virtual hierarchies of an endpoint from hosts that are connected based on multi-root input/output virtualization (MR-IOV). A management controller may instruct a SHPC to generate a PCI packet that specifies a particular virtual hierarchy to disconnect from a particular host. An upstream port connected to the host and the SHPC receives the PCI packet and uses a header that identifies the virtual endpoint in the packet to index into a routing table to identify a downstream port in the distributed switch that is connected to the endpoint. Once the PCI packet traverses the switch and arrives at the downstream port, the downstream port changes routing logic which logically disconnects the host from the specified virtual hierarchy.Type: ApplicationFiled: June 20, 2012Publication date: December 6, 2012Applicant: International Business Machines CorporationInventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink
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Patent number: 8271710Abstract: In an embodiment, a command is received that requests movement of ownership of a target device from an origin compute element to a destination compute element. From the origin compute element, a translation of a virtual bridge identifier to a first secondary bus identifier, a first subordinate bus identifier, and a first MMIO bus address range is removed. To the destination compute element, a translation of the target virtual bridge identifier to a second secondary bus identifier, a second subordinate bus identifier, and a second MMIO bus address range is added. From a south chip that comprises the target virtual bridge, a translation of the target virtual bridge identifier to an identifier of the origin compute element is removed. To the south chip, a translation of the target virtual bridge identifier to an identifier of the destination compute element is added.Type: GrantFiled: June 24, 2010Date of Patent: September 18, 2012Assignee: International Business Machines CorporationInventors: William J. Armstrong, Scott N. Dunham, David R. Engebretsen, Ronald E. Freking, Mehul M. Shah, Steven M. Thurber, Curtis C. Wollbrink