Abstract: A method for scanning a partially functional chip. The method may include applying a failed core map to the partially functional chip, bypassing at least one failed core scan chain, based on contents of the failed core map. The method may also include performing comparisons of scan status information to the failed core map and inhibiting movement of scan data of at least one failed core, based on results of the comparisons.

Abstract: A method for scanning a partially functional chip. The method may include applying a failed core map to the partially functional chip, bypassing at least one failed core scan chain, based on contents of the failed core map. The method may also include performing comparisons of scan status information to the failed core map and inhibiting movement of scan data of at least one failed core, based on results of the comparisons.

Abstract: A method for scanning a partially functional chip. The method may include applying a failed core map to the partially functional chip, bypassing at least one failed core scan chain, based on contents of the failed core map. The method may also include performing comparisons of scan status information to the failed core map and inhibiting movement of scan data of at least one failed core, based on results of the comparisons.

Abstract: A system is disclosed for concurrently processing order sensitive data packets. A first data packet from a plurality of sequentially ordered data packets is directed to a first offload engine. A second data packet from the plurality of sequentially ordered data packets is directed to a second offload engine, wherein the second data packet is sequentially subsequent to the first data packet. The second offload engine receives information from the first offload engine, wherein the information reflects that the first offload engine is processing the first data packet. Based on the information received at the second offload engine, the second offload engine processes the second data packet so that critical events in the processing of the first data packet by the first offload engine occur prior to critical events in the processing of the second data packet by the second offload engine.

Abstract: A method for scanning a partially functional chip. The method may include applying a failed core map to the partially functional chip, bypassing at least one failed core scan chain, based on contents of the failed core map. The method may also include performing comparisons of scan status information to the failed core map and inhibiting movement of scan data of at least one failed core, based on results of the comparisons.

Abstract: A system is disclosed for fetching control instructions for a direct memory access (DMA) engine shared between a plurality of threads. For a data transfer from a first thread by a DMA engine, the DMA engine fetches and processes a predetermined number of control instructions (or work queue elements) for the data transfer, each of the control instructions including an amount and location of data to transfer. The DMA engine determines a total amount of data transferred as a result of the data transfer. The DMA engine then determines a difference between the total amount of data transferred and a threshold amount of data, wherein the threshold amount of data indicates a preferred amount of data to be transferred for the first thread. The predetermined number of control instructions to fetch is updated based on the determined difference.

Abstract: A system is disclosed for fetching control instructions for a direct memory access (DMA) engine shared between a plurality of threads. For a data transfer from a first thread by a DMA engine, the DMA engine fetches and processes a predetermined number of control instructions (or work queue elements) for the data transfer, each of the control instructions including an amount and location of data to transfer. The DMA engine determines a total amount of data transferred as a result of the data transfer. The DMA engine then determines a difference between the total amount of data transferred and a threshold amount of data, wherein the threshold amount of data indicates a preferred amount of data to be transferred for the first thread. The predetermined number of control instructions to fetch is updated based on the determined difference.

Abstract: A system is disclosed for concurrently processing order sensitive data packets. A first data packet from a plurality of sequentially ordered data packets is directed to a first offload engine. A second data packet from the plurality of sequentially ordered data packets is directed to a second offload engine, wherein the second data packet is sequentially subsequent to the first data packet. The second offload engine receives information from the first offload engine, wherein the information reflects that the first offload engine is processing the first data packet. Based on the information received at the second offload engine, the second offload engine processes the second data packet so that critical events in the processing of the first data packet by the first offload engine occur prior to critical events in the processing of the second data packet by the second offload engine.

Abstract: Performance counters are provided for virtualized network interfaces of communications networks, while minimizing the use of hardware resources. A virtualized network interface includes physical resources, as well as logical resources. Dedicated performance counters are provided for the physical resources of the virtualized network interface, as well as for logical partitions coupled to that interface, while non-dedicated performance counters are provided for the logical resources. This enables the provision of performance counters for virtualized network interfaces, while minimizing hardware resources consumed by those interfaces.

Abstract: An information processing system is provided which includes a plurality of system resources, and an event queue having a maximum number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events in the event queue, wherein the entries are limited to a predetermined number of active entries in the event queue per each type of event per each of the system resources. In a particular embodiment, the number of entries per each type of event for each of the system resources is limited to one.

Abstract: A method of speculative credit data flow control includes defining a low watermark value as a function of a number of open buffers in a receiving unit; receiving a data packet from a sending unit; determining whether the data packet includes a packet delay indicator; defining a first speculative credit value responsive to receiving the packet delay indicator; defining a second speculative credit value as a function of the first speculative credit value added to a regular credit value; generating a flow control packet including the second speculative credit value; and sending the flow control packet to the sending unit.

Abstract: A method of speculative credit data flow control includes defining a low watermark value as a function of a number of open buffers in a receiving unit; receiving a data packet from a sending unit; determining whether the data packet includes a packet delay indicator; defining a first speculative credit value responsive to receiving the packet delay indicator; defining a second speculative credit value as a function of the first speculative credit value added to a regular credit value; generating a flow control packet including the second speculative credit value; and sending the flow control packet to the sending unit.

Abstract: Systems, methods, and software products for moving and/or resizing a producer-consumer queue in memory without stopping all activity is provided so that no data is lost or accidentally duplicated during the move. There is a software consumer and a hardware producer, such as a host channel adapter.

Abstract: Performance counters are provided for virtualized network interfaces of communications networks, while minimizing the use of hardware resources. A virtualized network interface includes physical resources, as well as logical resources. Dedicated performance counters are provided for the physical resources of the virtualized network interface, as well as for logical partitions coupled to that interface, while non-dedicated performance counters are provided for the logical resources. This enables the provision of performance counters for virtualized network interfaces, while minimizing hardware resources consumed by those interfaces.

Abstract: Performance counters are provided for virtualized network interfaces of communications networks, while minimizing the use of hardware resources. A virtualized network interface includes physical resources, as well as logical resources. Dedicated performance counters are provided for the physical resources of the virtualized network interface, as well as for logical partitions coupled to that interface, while non-dedicated performance counters are provided for the logical resources. This enables the provision of performance counters for virtualized network interfaces, while minimizing hardware resources consumed by those interfaces.

Abstract: An information processing system is provided which includes a plurality of system resources, and an event queue having a maximum number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events in the event queue, wherein the entries are limited to a predetermined number of active entries in the event queue per each type of event per each of the system resources. In a particular embodiment, the number of entries per each type of event for each of the system resources is limited to one.

Abstract: Systems, methods, and software products for moving and/or resizing a producer-consumer queue in memory without stopping all activity is provided so that no data is lost or accidentally duplicated during the move. There is a software consumer and a hardware producer, such as a host channel adapter.

Abstract: An information processing system is provided which includes a plurality of system resources, and an event queue having a predetermined number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events in the event queue, wherein the entries are limited to a predetermined number of active entries in the event queue per each type of event per each of the system resources. In a particular embodiment, the number of entries per each type of event for each of the system resources is limited to one.

Abstract: Systems, methods, and software products for moving and/or resizing a producer-consumer queue in memory without stopping all activity is provided so that no data is lost or accidentally duplicated during the move. There is a software consumer and a hardware producer, such as a host channel adapter.

Abstract: A method for coalescing acknowledge packets within a server is disclosed. A Read Request queue having multiple queue pair entries is provided. Each of the queue pair entries includes a packet sequence number (PSN) field and an indicator field. In response to a receipt of a Write Request packet, an indicator field of a queue pair entry is set to indicate that an Ack packet has been queued within the queue pair entry, and a PSN of the Write Request packet is written into a PSN field of the queue pair entry. In addition, a Queue Write Pointer is maintained to point to the queue pair entry. In response to a receipt of a Read Request packet, the indicator field of the queue pair entry is set to indicate that a Read Request packet has been queued within the queue pair entry, and a PSN of the Read Request packet is written into the PSN field of the queue pair entry. Also, the Queue Write Pointer is advanced to point to a queue pair entry that is subsequent to the queue pair entry.