Abstract: A fuse link (50) is formed using a method which offers greater scalability of the general conductor system used to wire the device. An oxide mask (36) having the shape of a desired fuse link is formed over a thin metallization layer (34). A barrier layer (38) is formed over the thin metallization layer (34). A conductive layer (40) is formed over the barrier layer (38). A photoresist mask (42) supplied to the conductive layer (40), and the conductive layer is etched to formed interconnects (44, 46). Subsequently, the barrier layer (38) and thin metallization layer (34) are etched, thus rendering a fuse link (50) between interconnects (44, 46) under the oxide mask (36).

Abstract: A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar.

Abstract: A method of interconnecting metal layers in integrated circuits separated by an intermediate dielectric layer by forming first and pillar layers of metal, etching the pillar layer to form a pillar of electrically conducting material and etching the first level to form the first level lead. A layer of dielectric is applied to cover the pillar and first level lead. A layer of photoresist is deposited over the dielectric with a spin on technique to form a planar surface. The dielectric and photoresist are etched back with an equal etch rate until a top portion of the pillar is exposed. A second level lead is formed atop the pillar and planar top surface of the dielectric.

Abstract: A fuse link (50) is formed using a method which offers greater scalability of the general conductor system used to wire the device. An oxide mask (36) having the shape of a desired fuse link is formed over a thin metallization layer (34). A barrier layer (38) is formed over the thin metallization layer (34). A conductive layer (40) is formed over the barrier layer (38). A photoresist mask (42) supplied to the conductive layer (40), and the conductive layer is etched to formed interconnects (44, 46). Subsequently, the barrier layer (38) and thin metallization layer (34) are etched, thus rendering a fuse link (50) between interconnects (44, 46) under the oxide mask (36).

Abstract: A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of the platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar.

Abstract: A method of forming double polysilicon contacts to underlying diffused regions of a semiconductor body which includes forming first and second level electrically conductive silicon layers over the body which contact respective first and second diffused regions of the body. The diffused regions are formed such that said first diffused region is ringed by said second diffused region. The second silicon layer thus overlaps the first silicon layer. The top surfaces of the first and second silicon layers are silicided such that the silicide formed over the first silicon layer is aligned with the edge of the second silicon layer.

Abstract: A method for forming contact vias in order to make electrical connection between conductive interconnection layers is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar.