Abstract: An improved sliding window dictionary-based compression method limits the data within the sliding window searched to data strings occurring at each discrete match location within a plurality of predefined discrete match locations, the plurality of predefined discrete match locations comprising a set of non-continuous data positions within the window of data.

Abstract: An improved sliding window dictionary-based compression method limits the data within the sliding window searched to data strings occurring at each discrete match location within a plurality of predefined discrete match locations, the plurality of predefined discrete match locations comprising a set of non-continuous data positions within the window of data.

Abstract: A run length codeword system which has a set of codewords, each codeword being one byte. The first codeword of a run is divided into a 4-bit code part and 4 bits of printing hints. The code part specifies the source of the data, and the format of the remaining bytes in the run. The remaining one or two codewords specify the number of remaining data bytes in the run, or color values.

Abstract: A run length codeword system which has a set of codewords, each codeword being one byte. The first codeword of a run is divided into a 4-bit code part and 4 bits of printing hints. The code part specifies the source of the data, and the format of the remaining bytes in the run. The remaining one or two codewords specify the number of remaining data bytes in the run, or color values.

Abstract: A process of loading an image in the form of a bit map into a memory which can transfer data words in burst mode in either row or column direction. First, the memory is divided into two sections with odd words stored in one section, even in the other, which allows ping pong buffers to be reading one word from memory while the next is being accessed. Also, the page height is set to be an odd number of words. Therefore, when the entire page is read in or out, successive words in either the row or column direction will always be alternately odd and even. If a partial image is read into the memory, this odd and even relationship will also hold. If an image with an even number of rows is read in, in order to preserve the sequential odd-even sequence, in every other column of the original data successive words are swapped so that the word order becomes 1, 0, 3, 2, etc. Then the addresses are also generated in staggered order, so that the words go into the correct location in memory.

Abstract: A layered document services architecture facilitating operation and interconnection of electronic printing systems with both resident and non-resident work inputs.

Abstract: A system for maintaining data consistency among distributed processors, each having its associated cache memory. A processor addresses data in its cache by specifying the virtual address. The cache will search its cells for the data associatively. Each cell has a virtual address, a real address, flags and a plurality of associated data words. If there is no hit on the virtual address supplied by the processor, a map processor supplies the equivalent real address which the cache uses to access the data from another cache if one has it, or else from real memory. When a processor writes into a data word in the cache, the cache will update all other caches that share the data before allowing the write to the local cache.

Abstract: A circuit to encode image data. The circuit receives image data in four bit nibbles which are either all-zero nibbles or terminating nibbles containing at least one non-zero bit. The circuit output is a series of code words, each a multiple of four bits and up to twenty-four bits long, packed into eight bit output words. Each code word contains a first part containing a run length specifying the number of received all-zero nibbles and a second part specifying the bit pattern of the terminating nibble. The circuit uses PROMs for the look-up and control elements and a pipeline of registers to allow high speed operation.

Abstract: A circuit for controlling the clock rate separately for each facet of a polygon used in a laser driven raster output scanner. The clock rate for facet #0 is servoed using a first order integrator (11) driven by a digital correction circuit which compares the actual number of pulses against the required number, and produces therefrom an analog correction pulse width which is applied to the integrator (11). A second order integrator (19) is used to compensate for leakage of charge from the parallel capacitor of the first order integrator (11), to improve performance. The remaining facets are then corrected for by assigning to each an individual correction voltage. This correction voltage is generated by counting clock pulses for each additional facet and using these pulse totals to generate individual analog correction voltages which are added to, or subtracted from the facet #0 voltage in an adder (18) which combines the facet #0 correction voltage with each individual voltage in sequence.

Abstract: An adapter is provided as an interface between a raster output scanning printer and an electronic image processor which formats digital information for use by the printer in creating printed images. The adapter accepts digital pulses through a structured array of communication lines from the electronic image processor. Each line is dedicated to the provision of certain video or control information which may be utilized by any one of a number of different raster output scanning printers. The electronic image processor is indifferent to the identity of the type of printer to which information is provided as the adapter serves to manipulate the data provided by the electronic image processor in a manner suitable to control the particular printer employed. The adapter is sensitive to the scanning cycles of the printer and accommodates deviations in scan time to increase or decrease the rate of provision of video information in accordance with fluctuations in printer motor speed.

Abstract: A circuit and method for the high speed generation and comparison of Hamming codes to enable the correction of an error burst is described. The circuit generates or compares n Hamming codes simultaneously with the data field transmission. Each code word is associated with a data field word comprising every n.sup.th bit. The resultant system corrects error bursts of up to n bits.Additional circuitry is included to enable the correction of error bits in parallel, increasing the system bandwidth.

Abstract: System and method for parallel decoding of character data in run length format to produce data in dot matrix form for presentation to a display device. The data for successive runs is stored in registers and processed in parallel to provide address data for memory devices programmed to deliver predetermined output data patterns in response to the address data.

Abstract: High resolution character generator for producing rows of characters to be scanned on a display medium. Input data defining characters to be printed in ordered rows of text is sorted to provide specifications for the characters which being on each successive scan line. These specifications are stored initially in an input buffer, and specifications for characters which have been partially printed in a previous scan line are stored in an active character buffer. For each scan line, the character specifications are read first from the active character buffer and then from the input buffer until an end of line specifier is reached. For each character specification received, a font memory containing data defining the characters is cycled. The data from the font memory is decoded and presented to the display medium on a line by line basis.