Abstract: A method and arrangement for transferring an indeterminate quantity of data from a target data bus to a requesting data bus. A memory block read command is provided to the target bus by an initiating device coupled to an initiating bus. Successive data segments are repeatedly transferred from the target device into a data buffer which is coupled between the initiating and target buses. The data segments are concurrently transferred from the data buffer to the initiating bus while other data segments are being transferred from the target bus into the data buffer. The transfer is terminated upon receipt of the entire desired data block at the initiating bus, and any read-ahead data remaining in the data buffer after this termination is discarded. The concurrent data transfer is allowed when the memory block read command is not in a delayed completion state, and the command response and requested data are next in the response queue.

Abstract: An arrangement for providing command responses in a sequence that is independent of the sequence that commands are initiated by an initiating bus to a target bus. A first memory array stores commands from the initiating bus in a first sequence, and provides the commands to the target bus in a first sequence. Multiple delayed completion registers are provided, each to receive and store one of the commands entered into the first memory array. The delayed completion registers re-enter its corresponding stored command into the first memory array when a request is received to reissue the command. A second memory array stores command responses in a second sequence that relates to the order that their corresponding commands were successfully completed on the target bus.

Abstract: A bridge circuit passes digital information between a primary PCI bus and a secondary PCI bus with increased throughput. The PCI busses carry digital information using respective clock signals having a known minimum skew therebetween. The interface bridge circuit includes primary and secondary PCI bus interfaces configured and arranged to communicate with the primary and secondary PCI busses respectively, and a memory buffer configured and arranged to store the digital information and to be accessed by the primary and secondary PCI bus interfaces. Further, a programmable configuration register is configurable in response to digital configure information received from the primary bus, and is adapted to provide an enable signal to one of the primary PCI bus interface and the secondary PCI bus interface. The enable signal indicates that the digital information is ready in the memory buffer for access by the one of the primary PCI bus interface and the secondary PCI bus interface.

Abstract: An arrangement for transferring information between initiating and target buses, using contiguous command buffering and target bus command decoding. A bus interface bridge circuit includes an initiating bus interface which outputs a plurality of commands, where each of the commands includes a corresponding code. A memory queue is coupled to the initiating bus interface to receive the commands, and to contiguously store the commands into the registers of the queue. A target bus interface is coupled to the output of the memory queue to successively receive the commands. The commands are then executed at targeted devices in accordance with their corresponding codes. A method for transferring commands from an initiating bus to a target bus using contiguous command buffering and target bus command decoding is also provided.

Abstract: In a data processing system that uses segmentation and paging to access data information such as in a virtual memory machine, the cache store need not be entirely cleared each time an I/O operation is performed or each time the data in the cache has a possibility of being incorrect. With segmentation and paging, only a portion of the cache store need be cleared when a new page is obtained from the virtual memory. The entire cache store is cleared only when a new segment is indicated by the instruction. The cache store is selectively cleared of the information from the page whose data information is no longer needed by addressing each level of an associative tag directory to the cache store. The columns of each level are compared to the page address and if a comparison is signaled that column of the addressed level is cleared by clearing the flag indicating the full status of the column in the addressed level. Each level of the tag directory is addressed.