Patents by Inventor Ronald F. Kaminsky

Ronald F. Kaminsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Adaptive routing for correcting die placement errors
    Patent number: 11652008
    Abstract: A method includes, receiving a layout design of at least part of an electronic module, the design specifying at least (i) an electronic device coupled to at least a substrate, and (ii) an electrical trace that is connected to the electronic device and has a designed route. A digital input, which represents at least part of an actual electronic module that was manufactured in accordance with the layout design but without at least a portion of the electrical trace, is received. An error in coupling the electronic device to the substrate, relative to the layout design, is estimated based on the digital input. An actual route that corrects the estimated error, is calculated for at least the portion of the electrical trace. At least the portion of the electrical trace is formed on the substrate of the actual electronic module, along the actual route instead of the designed route.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 16, 2023
    Assignee: Orbotech Ltd.
    Inventors: Ram Oron, Michael Burdinov, Elad Goshen, Ronald F. Kaminsky, Gonen Raveh
  • Adaptive Routing for Correcting Die Placement Errors
    Publication number: 20220012405
    Abstract: A method includes, receiving a layout design of at least part of an electronic module, the design specifying at least (i) an electronic device coupled to at least a substrate, and (ii) an electrical trace that is connected to the electronic device and has a designed route. A digital input, which represents at least part of an actual electronic module that was manufactured in accordance with the layout design but without at least a portion of the electrical trace, is received. An error in coupling the electronic device to the substrate, relative to the layout design, is estimated based on the digital input. An actual route that corrects the estimated error, is calculated for at least the portion of the electrical trace. At least the portion of the electrical trace is formed on the substrate of the actual electronic module, along the actual route instead of the designed route.
    Type: Application
    Filed: October 2, 2019
    Publication date: January 13, 2022
    Inventors: Ram Oron, Michael Burdinov, Elad Goshen, Ronald F. Kaminsky, Gonen Raveh