Abstract: Various embodiments of the invention provide for an AC-coupling method and systems that utilize a nested loop circuit to generate a differential mode output that facilitates an offset compensation and a common mode output that facilitates DC-biasing of an active circuit. In embodiments, the nested loop circuit comprises a differential amplifier and a differential mode loop that generates a differential mode output and a common mode loop that uses a common mode voltage and a reference voltage to generate the common mode output.

Abstract: A microprocessor controlled data recovery unit with an adjustable sampling and signal comparison level. The data recovery unit includes a data channel and a monitor channel. The monitor channel samples an incoming data stream in a varying manner. The results of the sampling in the monitor channel are used to adjust the sampling and comparing of the signal in the data channel. The data recovery unit includes a PLL based clock recovery unit in one embodiment, and in another embodiment the clock signal is derived by the microprocessor.

Abstract: A microprocessor controlled data recovery unit with an adjustable sampling and signal comparison level. The data recovery unit includes a data channel and a monitor channel. The monitor channel samples an incoming data stream in a varying manner. The results of the sampling in the monitor channel are used to adjust the sampling and comparing of the signal in the data channel. The data recovery unit includes a PLL based clock recovery unit in one embodiment, and in another embodiment the clock signal is derived by the microprocessor.

Abstract: An adjustable frequency oscillator with a wide tuning range which can be voltage or current controlled. A maximum tuning per feedback current is obtained by phase shifting a feedback signal by approximately 90 degrees with respect to the oscillating output signal, which is internally generated by the adjustable frequency oscillator. Over the frequency range of operation, the oscillation frequency of the oscillating output signal is linearly controllable. The adjustable frequency oscillator is also implemented as a ring oscillator and/or an oscillator with ranging.

Abstract: A microprocessor controlled data recovery unit with an adjustable sampling and signal comparison level. The data recovery unit includes a data channel and a monitor channel. The monitor channel samples an incoming data stream in a varying manner. The results of the sampling in the monitor channel are used to adjust the sampling and comparing of the signal in the data channel. The data recovery unit includes a PLL based clock recovery unit in one embodiment, and in another embodiment the clock signal is derived by the microprocessor.

Abstract: The present disclosure encompasses the use of a current mirror to control the trip point for a power-on-reset circuit. The current mirror is designed to turn on at a multiple of a transistor threshold voltage V.sub.t. The power-on-reset circuit asserts a power-on signal in response to mirror current provided by the current mirror when the supply voltage ramps up above the V.sub.t multiple. Since the transistor threshold voltage may be tightly controlled during the fabrication process, the trip point for the power-on-reset circuit may be precisely and accurately adjusted to match the minimum operating supply voltage level specified for an integrated circuit device such as a microprocessor. Also, a feedback path may be provided in the power-on-reset circuit to turn off the current mirror once the power-on signal is asserted so that there is no current draw in the power-on-circuit for static conditions.

Abstract: The present invention encompasses the use of multiple feedback paths in a clock source for an integrated circuit device to maintain phase lock to an external clock. It is further contemplated by the present invention that feedback paths are provided from the internal clock distribution path and from a matching path that approximates the delay of the clock distribution path. The matching path may comprise a delay locked loop. Feedback from the clock distribution path is used in normal operation and feedback from the matching path is used when the internal clock distribution path is disabled. The clock source of the present invention also may implement power management functions.

Abstract: A phase-frequency detector provides a decreased blind spot near 360.degree. of phase error and a resulting increased phase error detection range. In one embodiment, the phase-frequency detector includes two latches that are set in response to the detection of positive transitions in respective input clock signals. A reset controller resets both latches when they both get set. The duration and sequence of the latch states are thereby indicative of phase errors between the input clock signals. Two edge-triggered pulse generators provide a sustained indication of a detected positive transition in the respective input clock signals. When the time duration of the sustained indications is set equal to the reset time required by the latches and reset controller, the blind spot of the phase-frequency detector is largely eliminated.

Abstract: A differential comparator is provided with an extended input range. In one embodiment, a differential amplifier is provided with a differential input buffer that allows for differential detection even with input voltage signal levels that extend two or more volts beyond the power supply voltage. A first transistor and a first resistor coupled in series are coupled in parallel with a second transistor and a second series resistor. The transistor drain terminals are both coupled to the power supply voltage, and a current source draws current from the common node of the resistors. Input voltages are supplied to the gates of the transistors, and the differential output voltages are provided from the transistor source terminals. A differential amplifier receives the differential output voltages and provides a single output voltage.

Abstract: A clock frequency detector is provided having a precise trip frequency which is insensitive to power supply variations. In one embodiment, the clock frequency detector employs a current source to discharge a capacitor at a constant rate and a gated current source to charge the capacitor at a frequency-dependent rate. If the charge rate exceeds the discharge rate, the capacitor will charge and an output signal is asserted. The gated current source is controlled by an edge-triggered pulse generator which generates pulses of a precise width in response to edges in the input clock signal. To create these pulses, the pulse generator produces an inverted clock signal with delayed transitions and combined this signal with the clock signal. The delayed transitions are created using a capacitor which is charged by a current source. The capacitor is provided with a shunt transistor which drains the charge from the capacitor whenever the clock signal is asserted.