Patents by Inventor Ronald Frank Kolc
Ronald Frank Kolc has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6733711Abstract: There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.Type: GrantFiled: March 14, 2003Date of Patent: May 11, 2004Assignee: General Electric CompanyInventors: Kevin Matthew Durocher, Ernest Wayne Balch, Vikram B. Krishnamurthy, Richard Joseph Saia, Herbert Stanley Cole, Ronald Frank Kolc
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Patent number: 6730533Abstract: There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.Type: GrantFiled: March 14, 2003Date of Patent: May 4, 2004Assignee: General Electric CompanyInventors: Kevin Matthew Durocher, Ernest Wayne Balch, Vikram B. Krishnamurthy, Richard Joseph Saia, Herbert Stanley Cole, Ronald Frank Kolc
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Patent number: 6614103Abstract: There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.Type: GrantFiled: September 1, 2000Date of Patent: September 2, 2003Assignee: General Electric CompanyInventors: Kevin Matthew Durocher, Ernest Wayne Balch, Vikram B. Krishnamurthy, Richard Joseph Saia, Herbert Stanley Cole, Ronald Frank Kolc
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Publication number: 20030160256Abstract: There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.Type: ApplicationFiled: March 14, 2003Publication date: August 28, 2003Applicant: General Electric CompanyInventors: Kevin Matthew Durocher, Ernest Wayne Balch, Vikram B. Krishnamurthy, Richard Joseph Saia, Herbert Stanley Cole, Ronald Frank Kolc
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Publication number: 20030153108Abstract: There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.Type: ApplicationFiled: March 14, 2003Publication date: August 14, 2003Applicant: General Electric CompanyInventors: Kevin Matthew Durocher, Ernest Wayne Balch, Vikram B. Krishnamurthy, Richard Joesph Saia, Herbert Stanley Cole, Ronald Frank Kolc
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Publication number: 20030057515Abstract: One type of electronic interface structure includes a base; at least one elastomeric island supported by the base; and patterned metallization overlying the at least one elastomeric island and including at least one floating pad at least partially overlying the at least one elastomeric island. Another type of electronic interface structure includes a base; a first dielectric layer overlying the base and having at least one first dielectric layer opening therein; a second dielectric layer overlying the first dielectric layer; and patterned metallization overlying the second dielectric layer and including at least one floating pad at least partially overlying the at least one opening.Type: ApplicationFiled: November 5, 2002Publication date: March 27, 2003Inventors: Raymond Albert Fillion, Robert John Wojnarowski, Ronald Frank Kolc
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Patent number: 6507113Abstract: One type of electronic interface structure includes a base; at least one elastomeric island supported by the base; and patterned metallization overlying the at least one elastomeric island and including at least one floating pad at least partially overlying the at least one elastomeric island. Another type of electronic interface structure includes a base; a first dielectric layer overlying the base and having at least one first dielectric layer opening therein; a second dielectric layer overlying the first dielectric layer; and patterned metallization overlying the second dielectric layer and including at least one floating pad at least partially overlying the at least one opening.Type: GrantFiled: November 19, 1999Date of Patent: January 14, 2003Assignee: General Electric CompanyInventors: Raymond Albert Fillion, Robert John Wojnarowski, Ronald Frank Kolc
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Patent number: 6396153Abstract: One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad.Type: GrantFiled: January 25, 2001Date of Patent: May 28, 2002Assignee: General Electric CompanyInventors: Raymond Albert Fillion, Ernest Wayne Balch, Ronald Frank Kolc, William Edward Burdick, Jr., Robert John Wojnarowski, Leonard Richard Douglas, Thomas Bert Gorczyca
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Publication number: 20010009779Abstract: One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad.Type: ApplicationFiled: January 25, 2001Publication date: July 26, 2001Inventors: Raymond Albert Fillion, Ernest Wayne Balch, Ronald Frank Kolc, William Edward Burdick, Robert John Wojnarowski, Leonard Richard Douglas, Thomas Bert Gorczyca
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Patent number: 6242282Abstract: One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad.Type: GrantFiled: October 4, 1999Date of Patent: June 5, 2001Assignee: General Electric CompanyInventors: Raymond Albert Fillion, Ernest Wayne Balch, Ronald Frank Kolc, William Edward Burdick, Jr., Robert John Wojnarowski, Leonard Richard Douglas, Thomas Bert Gorczyca
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Patent number: 6239482Abstract: An integrated circuit package includes at least one integrated circuit element coupled to a polymer film; a window frame coupled to the polymer film and surrounding the at least one integrated circuit element; and encapsulant material positioned between the at least one integrated circuit element and the window frame.Type: GrantFiled: June 21, 1999Date of Patent: May 29, 2001Assignee: General Electric CompanyInventors: Raymond Albert Fillion, William Edward Burdick, Jr., Ronald Frank Kolc, James Wilson Rose, Glenn Scott Claydon
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Patent number: 6239980Abstract: A circuit design is logically partitioned into a plurality of blocks. As a first hierarchial assembly level, the blocks are fabricated as individual submodules each including at least one electronic component with component connection pads on a top surface, and a first interconnect structure including at least one interconnect layer bonded to the top surfaces, and interconnecting selected ones of the component connection pads. Submodule connection pads are provided on upper surfaces of the submodules. As a second hierarchial assembly level, a second interconnect structure is bonded to the upper surfaces and interconnects selected ones of the submodule connection pads.Type: GrantFiled: August 31, 1998Date of Patent: May 29, 2001Assignee: General Electric CompanyInventors: Raymond Albert Fillion, Wolfgang Daum, Ronald Frank Kolc, Donald William Kuk, Rob Ert John Wojnarowski
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Patent number: 5857858Abstract: Connection elements which, for example, may be used to facilitate interconnection to and stacking of electronic assemblies or may include an elongated conductive core, such as a wire or a hollow tube structure, coated with a layer of elastomeric material containing conductive particle such that the elastomeric material is conductive at least when compressed. The substrates of multi-chip modules (MCMs) have electrical connection sites in the form of metal-lined channels in the substrate edges, and the connection elements are pressed into the channels. Separate compression or clamping elements may be employed to enhance conductivity, as well as to facilitate external connections. The elongated conductive core may take the form of a hollow tube structure which may be expanded under internal pressure to compress the layer of elastomeric material. The compression elements may take the form of printed circuit boards.Type: GrantFiled: December 23, 1996Date of Patent: January 12, 1999Assignee: General Electric CompanyInventors: Bernard Gorowitz, Robert John Wojnarowski, Ronald Frank Kolc