Abstract: An integrated circuit (IC) structure includes a back end of line (BEOL) stack on a substrate, the BEOL stack having a plurality of metal layers therein and a plurality of inter-level dielectric (ILD) layers therein. The plurality of metal layers includes a lowermost metal layer and an uppermost metal layer. A pair of metal guard structures proximate a perimeter of the BEOL stack concentrically surrounds the active circuitry. Each metal guard structure includes a continuous metal fill between the lowermost metal layer and the uppermost metal layer of the plurality of metal layers. A set of interdigitating conductive elements within one of the plurality of metal layers includes a first plurality of conductive elements electrically coupled to one of the pair of metal guard structures interdigitating with a second plurality of conductive elements electrically coupled to the other of the pair of metal guard structures.

Abstract: An integrated circuit (IC) structure includes a back end of line (BEOL) stack on a substrate, the BEOL stack having a plurality of metal layers therein and a plurality of inter-level dielectric (ILD) layers therein. The plurality of metal layers includes a lowermost metal layer and an uppermost metal layer. A pair of metal guard structures proximate a perimeter of the BEOL stack concentrically surrounds the active circuitry. Each metal guard structure includes a continuous metal fill between the lowermost metal layer and the uppermost metal layer of the plurality of metal layers. A set of interdigitating conductive elements within one of the plurality of metal layers includes a first plurality of conductive elements electrically coupled to one of the pair of metal guard structures interdigitating with a second plurality of conductive elements electrically coupled to the other of the pair of metal guard structures.

Abstract: An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test. The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt around the decoder upon failure of the device under test.

Abstract: Interconnect structures for a security application and methods of forming an interconnect structure for a security application. A sacrificial masking layer is formed that includes a plurality of particles arranged with a random distribution. An etch mask is formed using the sacrificial masking layer. A hardmask is etched while masked by the etch mask to define a plurality of mask features arranged with the random distribution. A dielectric layer is etched while masked by the hardmask to form a plurality of openings in the dielectric layer that are arranged at the locations of the mask features. The openings in the dielectric layer are filled with a conductor to define a plurality of conductive features.

Abstract: An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test. The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt around the decoder upon failure of the device under test.

Abstract: Interconnect structures for a security application and methods of forming an interconnect structure for a security application. A sacrificial masking layer is formed that includes a plurality of particles arranged with a random distribution. An etch mask is formed using the sacrificial masking layer. A hardmask is etched while masked by the etch mask to define a plurality of mask features arranged with the random distribution. A dielectric layer is etched while masked by the hardmask to form a plurality of openings in the dielectric layer that are arranged at the locations of the mask features. The openings in the dielectric layer are filled with a conductor to define a plurality of conductive features.

Abstract: A method for analyzing circuit designs includes discretizing a design representation into pixel elements representative of a structure in the design and determining at least one property for each pixel element representing a portion of the design. Then, a response of the design is determined due to local properties across the design.

Abstract: A test circuit for testing semiconductors includes a plurality of at least first conductors and second conductors. The first and second conductors are operatively connected together by a plurality of conductive vias to form an open chain of alternating first and second conductors. A plurality of conductive taps are included, each of the taps being connected at a first end to a corresponding first conductor. The test circuit further includes a plurality of switching circuits, each of the switching circuits being operatively connected to a second end of a corresponding one of the conductive taps. Each of the switching circuits is configurable for selectively connecting the corresponding conductive tap to one of at least a first bus and a second bus in response to at least one control signal presented to the switching circuit, the first and second buses being connected to first and second bond pads, respectively.

Abstract: A method for determining the electromigration characteristics of a wiring structure in an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes configuring a defined test structure type for the integrated circuit device. The defined test structure type further includes a first line of wiring primarily disposed in a principal plane of a semiconductor substrate, and a second line of wiring connected to the first line of wiring. The second line of wiring is disposed in a secondary plane which is substantially parallel to the principal plane, with the first and second lines of wiring being connected by a via structure therebetween. A thermal coefficient of resistance for the first line of wiring and the via structure is determined, and a wafer-level stress condition is introduced in a first individual test structure of the defined test structure type.