Abstract: The Write/Erase lifetime of amorphous memory devices are extended by applying an erase pulse sequence having a first plurality of reset voltage pulses having a maximum amplitude less than the maximum threshold of the device to produce first amplitude current pulses and a second plurality of reset voltage pulses having a maximum amplitude greater than the maximum threshold to produce second amplitude current pulses having an amplitude substantially less than said current pulses. Constant current sources apply the two current pulses when the device threshold is below the maximum voltage amplitude of the first reset voltage pulses and only the second amplitude current pulses when the device threshold exceeds the maximum voltage amplitude of the first reset voltage pulses.

Abstract: The Write/Erase lifetimes of amorphous memory devices are extended by applying a multilevel erase pulse wherein the first stage has a current amplitude sufficient to heat the crystal filament to the phase change temperature but not to provide the energy for the phase change and erasure of the crystal structure and the second stage has a current amplitude sufficient to heat the filament to remove the crystal structure. Preferably the first stage current is equal to the write current and the second stage is equal to the write current times the ratio of the electrical conductivity of the amorphous conducting state to the apparent conductivity of the crystalline state.

Abstract: An amorphous memory cell operated to have a first logic state represented by a high resistance state, substantially no crystal structure and a first threshold level and a second logic state represented by a high resistance state, microcrystal structure and a threshold level lower than the first threshold level. The logic state is read by monitoring the electrical characteristic of the cell for a constant voltage read pulse at a time greater than the threshold switching delay duration for the first logic state and less than the threshold switching delay duration for the second logic state at the read pulse voltage.

Abstract: A memory cell, having a doped amorphous silicon layer, is formed on a thin layer of silicon alloy which is on a single crystal silicon substrate. The cell is programmed by applying a voltage between a surface contact and the substrate to cause a crystal column to form in the amorphous layer between the substrate and the contact by solid-phase epitaxial growth. A diode is formed between the contact and the substrate by the selection of impurity levels and conductivity type of the amorphous layer and substrate and the selection of the silicon alloy. The cross-sectional area of the column is selectable to provide a multi storage level cell.