Patents by Inventor Ronald George Dreslinski
Ronald George Dreslinski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10037295Abstract: An interconnect within an integrated circuit provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).Type: GrantFiled: December 2, 2016Date of Patent: July 31, 2018Assignee: The Regents of the University of MichiganInventors: Supreet Jeloka, Sandunmalee Nilmini Abeyratne, Ronald George Dreslinski, Reetuparna Das, Trevor Nigel Mudge, David Theodore Blaauw
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Publication number: 20170083471Abstract: An interconnect within an integrated circuit provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).Type: ApplicationFiled: December 2, 2016Publication date: March 23, 2017Inventors: Supreet JELOKA, Sandunmalee Nilmini ABEYRATNE, Ronald George DRESLINSKI, Reetuparna DAS, Trevor Nigel MUDGE, David Theodore BLAAUW
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Patent number: 9514074Abstract: An interconnect within an integrated circuit provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).Type: GrantFiled: July 12, 2013Date of Patent: December 6, 2016Assignee: The Regents of the University of MichiganInventors: Supreet Jeloka, Sandunmalee Nilmini Abeyratne, Ronald George Dreslinski, Reetuparna Das, Trevor Nigel Mudge, David Theodore Blaauw
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Publication number: 20150154045Abstract: A hardware transactional memory is provided within a multiprocessor system with coherency control and hardware transaction memory control circuitry that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data. The conflict data characterizes previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.Type: ApplicationFiled: February 10, 2015Publication date: June 4, 2015Inventors: Geoffrey Blake, Trevor Nigel Mudge, Nathan Yong Seng Chong, Ronald George Dreslinski, Stuart David Biles, Emre Özer
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Patent number: 8825955Abstract: A data processing apparatus has a cache with a data array and a tag array. The tag array stores address tag portions associated with the data values in the data array. The cache performs a tag lookup, comparing a tag portion of a received address with a set of tag entries in the tag array. The data array includes a partial tag store storing a partial tag value in association with each data entry. In parallel with the tag lookup, a partial tag value of the received address is compared with partial tag values stored in association with a set of data entries in said data array. A data value is read out if a match condition occurs. Exclusivity circuitry ensures that at most one partial tag value of said partial tag values stored in association with said set of data entries can generate said match condition.Type: GrantFiled: March 19, 2012Date of Patent: September 2, 2014Assignee: The Regents of the University of MichiganInventors: Faissal Mohamad Sleiman, Ronald George Dreslinski, Jr., Thomas Friedrich Wenisch
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Publication number: 20140019655Abstract: An interconnect 6 within an integrated circuit 2 provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).Type: ApplicationFiled: July 12, 2013Publication date: January 16, 2014Inventors: Supreet Jeloka, Sandunmalee Nilmini Abeyratne, Ronald George Dreslinski, Reetuparna Das, Trevor Nigel Mudge, David Theodore Blaauw
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Publication number: 20130132675Abstract: A data processing apparatus has a cache with a data array and a tag array. The tag array stores address tag portions associated with the data values in the data array. The cache performs a tag lookup, comparing a tag portion of a received address with a set of tag entries in the tag array. The data array includes a partial tag store storing a partial tag value in association with each data entry. In parallel with the tag lookup, a partial tag value of the received address is compared with partial tag values stored in association with a set of data entries in said data array. A data value is read out if a match condition occurs. Exclusivity circuitry ensures that at most one partial tag value of said partial tag values stored in association with said set of data entries can generate said match condition.Type: ApplicationFiled: March 19, 2012Publication date: May 23, 2013Applicant: The Regents of the University of MichiganInventors: Faissal Mohamad SLEIMAN, Ronald George Dreslinski, JR., Thomas Friedrich Wenisch
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Patent number: 8335122Abstract: A data processing apparatus is provided having a cache memory comprising a data storage array and a tag array and a cache controller coupled to the cache memory responsive to a cache access request from processing circuitry to perform cache look ups. The cache memory is arranged such that it has a first memory cell group configured to operate in a first voltage domain and a second memory cell group configured to operate in a second voltage domain that is different from the first voltage domain. A corresponding data processing method is also provided.Type: GrantFiled: November 12, 2008Date of Patent: December 18, 2012Assignee: The Regents of the University of MichiganInventors: Ronald George Dreslinski, Jr., Gregory Kengho Chen, Trevor Nigel Mudge, David Theodore Blaauw, Dennis Sylvester
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Patent number: 8108585Abstract: Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided that comprises a storage circuit programmable to store a routing value, and a transmission circuit. In a transmission mode of operation the transmission circuit is responsive to the routing value indicating that the data input path should be coupled to the data output path to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. Control circuitry is used to issue control signals to the crossbar cells, and during a configuration mode of operation the control circuitry re-utilizes at least one of the data output paths to program the storage circuitry of one or more of the crossbar cells.Type: GrantFiled: February 13, 2009Date of Patent: January 31, 2012Assignee: The Regents of the Universtiy of MichiganInventors: Sudhir Kumar Satpathy, David Theodore Blaauw, Trevor Nigel Mudge, Dennis Michael Sylvester, Ronald George Dreslinski, Jr.
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Publication number: 20090138658Abstract: A data processing apparatus is provided having a cache memory comprising a data storage array and a tag array and a cache controller coupled to the cache memory responsive to a cache access request from processing circuitry to perform cache look ups. The cache memory is arranged such that it has a first memory cell group configured to operate in a first voltage domain and a second memory cell group configured to operate in a second voltage domain that is different from the first voltage domain. A corresponding data processing method is also provided.Type: ApplicationFiled: November 12, 2008Publication date: May 28, 2009Applicant: The Regents of the University of MichiganInventors: Ronald George Dreslinski, JR., Gregory Kengho Chen, Trevor Nigel Mudge, David Theodore Blaauw, Dennis Sylvester
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Publication number: 20090138890Abstract: A hardware transactional memory 12, 14, 16, 18, 20 is provided within a multiprocessor 4, 6, 8, 10 system with coherency control and hardware transaction memory control circuitry 22 that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data 26, 28, 30. The conflict data characterises previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.Type: ApplicationFiled: November 20, 2008Publication date: May 28, 2009Applicant: ARM LIMITEDInventors: Geoffrey Blake, Trevor Nigel Mudge, Stuart David Biles, Nathan Yong Seng Chong, Emre Ozer, Ronald George Dreslinski