Abstract: A CMOS exclusive OR/NOR gate is implemented with cross coupled transistors of the same conductivity type for simultaneously providing both logic signals. The logic gate is characterized by a pair of cross-coupled transistors of the same conductivity type coupled to the outputs thereof for selectively reinforcing the output logic level. One use of the exclusive OR/NOR gate is illustrated by coupling the gate to a switched logic circuit to provide a full adder. Transmission gate steering logic is used to further enhance circuit speed.

Abstract: An improved analog CMOS comparator circuit is described. The improved circuit incorporates an additional CMOS device in the output stage of a conventional differential comparator. The additional device compensates for current imbalances which occur at relatively high common mode voltages thus allowing the improved comparator to operate over a wider range of common mode input voltages.

Abstract: An MOS full adder circuit having a sum circuit portion and a carry circuit portion is provided. In an embodiment utilizing transistors of opposite conductivity type, both the sum and carry circuits are symmetrical, thereby simplifying the physical layout of the full adder during fabrication.

Abstract: An X.times.Y bit array multiplier/accumulator circuit is provided for adding an input number having (X+Y) bits to an (X+Y) bit product of an X bit number and a Y bit number, where X and Y are integers. Modified Booth's algorithm is implemented with an array structure which maintains a regular and systematic structure. The array structure uses adders and multiplexers in a predetermined column and row arrangement. Propagation delay is minimized while utilizing the modified Booth's algorithm by using a sum skipping technique and by using inverting logic properties of adders. Sign bit extension is provided by additional logic circuitry and signed/unsigned modes of operation are provided.