Abstract: A frequency management scheme for a hybrid communications/positioning device, such as a cellular/GPS or other combined device, generates a local clock signal for the communications portion of the device, using a crystal oscillator or other part. The oscillator output may be delivered to a phase locked loop to drive a high-frequency clock for the cellular or other communications portion of the hybrid device. A processor may determine frequency error between the phase locked loop and base station or other reference, to derive a digital frequency tracking message. A Doppler search or other logical control message may likewise be communicated from the processor to a GPS or other positioning receiver. The GPS receiver circuitry may consequently adjust Doppler center, window width or other parameters to enhance time to first fix or other performance.

Abstract: A global positioning system (GPS) receiver (102) has a reference oscillator (114) for use in synthesizing signals for use in receiving and acquiring GPS satellite signals by a GPS downconverter (110). Upon manufacture of the receiver (204), the receiver is tested and a factory frequency offset of the oscillator is determined (206). It has been found that the heat used in reflowing the solder used to attach receiver components causes the operating frequency of oscillator devices, such as crystals, to shift considerably. In addition, during a brief period after manufacture of the receiver, the frequency of the oscillator shifts back towards its original operating frequency, and so much so that the narrow search window used to search for a GPS carrier is inadequate, and it is likely that the receiver would not locate the desired carrier signal.

Abstract: A frequency management scheme for a hybrid communications/positioning device, such as a cellular/GPS or other combined device, generates a local clock signal for the communications portion of the device, using a crystal oscillator or other part. The oscillator output may be delivered to a phase locked loop to drive a high-frequency clock for the cellular or other communications portion of the hybrid device. A processor may determine frequency error between the phase locked loop and base station or other reference, to derive a digital frequency tracking message. A Doppler search or other logical control message may likewise be communicated from the processor to a GPS or other positioning receiver. The GPS receiver circuitry may consequently adjust Doppler center, window width or other parameters to enhance time to first fix or other performance.

Abstract: A frequency management scheme for a hybrid communications/positioning device, such as a cellular/GPS or other combined device, generates a local clock signal for the communications portion of the device, using a crystal oscillator or other part. The oscillator output may be corrected by way of an automatic frequency control (AFC) circuit or software, to drive the frequency of that clock signal to a high accuracy. The base oscillator may be delivered to a phase locked loop to drive a high-frequency clock for the cellular or other communications portion of the hybrid device, which clock signal may also be frequency-converted to drive a GPS or other positioning receiver. The extraction of a base GPS clock from the radio frequency reference eliminates the need for a second oscillator or synthesizer for that portion of the hybrid device.

Abstract: A frequency generation circuit includes an oscillator (403), a comparator (413) coupled to the oscillator, a first divider (407) coupled to the comparator, a PLL (400) coupled to the first divider, a second divider (422) coupled to the PLL, a first multiplexor (409) coupled to the second divider, a third divider (408) coupled to the comparator and the first multiplexor, a second multiplexor (410) coupled to the comparator and the reference clock PLL, a fourth divider (411) coupled to the second multiplexor, a fifth divider (412) coupled to the comparator, and a seventh divider (450) coupled to the comparator. A method of operating a transceiver includes using the frequency generation circuit to provide a first clock signal, a second clock signal, a first reference frequency, and a second reference frequency for a first component, a second component, a third component, and a fourth component, respectively, of the transceiver.

Abstract: A phase lock loop (100) includes a dual-state charge pump (120) having a first current source (220), a second current source (230) coupled in series to the first current source, a third current source (240), a fourth current source (250) coupled in series to the third current source, and control circuitry (210) coupled to the first, second, third, and fourth current sources. The charge pump can be programmed to be in an adapt mode with large up and down currents or in a normal mode with small up and down currents. The duration of the adapt mode can be programmed by a timer. The phase lock loop has a wide loop bandwidth and a faster lock time during the adapt mode and a narrow loop bandwidth and less phase noise during the normal mode.

Abstract: A device having battery-save circuitry includes a power-on reset circuit (603), an OR-gate (604) coupled to the power-on reset circuit (603), a current-boost timer circuit (602) coupled to the OR-gate (604), a reference oscillator (403) with a start-up current mode enabled by the current-boost timer circuit (602), and a low current secondary reference oscillator (613). A method of operating the device includes operating the device in a battery-save mode and an active mode. A first clock signal is used as a microprocessor clock signal while operating the device in the battery-save mode, and a second or third clock signal is used as the microprocessor clock signal while operating the device in the active mode.