Abstract: A job submission technique includes a set of algorithms that provide automated workload selection to a batch processing system that has the ability to receive and run jobs on various computing resources simultaneously. The job submission technique provides for organizing workloads, assigning relative ratios between workloads, associating arbitrary workload validation algorithms with a workload or parent workload, associating arbitrary selection algorithms with a workload or workload group, defining high priority workloads that preserve fairness, and balancing the workload selection based on a current status of the batch system, validation status, and the workload ratios.

Abstract: A job submission technique includes a set of algorithms that provide automated workload selection to a batch processing system that has the ability to receive and run jobs on various computing resources simultaneously. The job submission technique provides for organizing workloads, assigning relative ratios between workloads, associating arbitrary workload validation algorithms with a workload or parent workload, associating arbitrary selection algorithms with a workload or workload group, defining high priority workloads that preserve fairness, and balancing the workload selection based on a current status of the batch system, validation status, and the workload ratios.

Abstract: A job submission method that presents a set of algorithms that provide automated workload selection to a batch processing system that has the ability to receive and run jobs on various computing resources simultaneously is provided. If all machines in the batch system are running jobs, a queue containing the extra jobs for execution results. For compute intensive workloads, such as chip design, an automated workload selection system software layer submits jobs to the batch processing system. This keeps the batch processing system continually full of useful work The job submission system provides for organizing workloads, assigning relative ratios between workloads, associating arbitrary workload validation algorithms with a workload or parent workload, associating arbitrary selection algorithms with a workload or workload group, defining high priority workloads that preserve fairness and balancing the workload selection based on current status of the batch system, validation status, and the workload ratios.

Abstract: A job submission method that presents a set of algorithms that provide automated workload selection to a batch processing system that has the ability to receive and run jobs on various computing resources simultaneously is provided. If all machines in the batch system are running jobs, a queue containing the extra jobs for execution results. For compute intensive workloads, such as chip design, an automated workload selection system software layer submits jobs to the batch processing system. This keeps the batch processing system continually full of useful work The job submission system provides for organizing workloads, assigning relative ratios between workloads, associating arbitrary workload validation algorithms with a workload or parent workload, associating arbitrary selection algorithms with a workload or workload group, defining high priority workloads that preserve fairness and balancing the workload selection based on current status of the batch system, validation status, and the workload ratios.

Abstract: A method for determining the configuration of a digital design first obtains a set of latch values of a plurality of latches within the digital design. A setting of a Dial instance is then determined based upon the set of latch values by reference to a configuration database that specifies a mapping table uniquely associating each a plurality of different settings of the Dial with a respective one of a plurality of different sets of latch values. The setting of the Dial instance is then output. In one embodiment, the setting of the Dial is contained in a simulation setup file utilized to configure a simulation model to a state approximating the state of the digital design represented by the set of latch values.

Abstract: A configuration database associated with a digital design stores at least one data structure defining a Dial instance and a mapping between each possible input value of the Dial instance and a respective output value. The output value controls which of a number of different possible latch values is placed in a configuration latch to configure a functional portion of a simulation model of the digital design. The configuration database further indicates an association between the Dial instance and the configuration latch. In response to a request specifying an input value for the Dial instance, the data structure in the configuration database is accessed to determine an output value for the Dial instance based upon the mapping. In addition, a latch value for the configuration latch is obtained based upon the output value and the association indicated by the configuration database. The latch value is then utilized to set the configuration latch in the simulation model.

Abstract: This mounting clamp is used as a truss adapter for support of fixtures, electrical and otherwise, from a truss ceiling. The clamp comprises a plate suspended by a pair of upstanding arms, each of which is formed by a bolt connected to an inverted U-shaped rectangular hanger member. The hangers and their associated bolts are inserted upwardly between the spaced beams of a bar joist from below and then the hangers are rotated 90 degrees before they are lowered into place to rest on both of the spaced beams, spreading the load, as the hanger arms are tightened to the plate. The plate carries a connector for mating to the object to be mounted. Leveling screws provide adjustment for orienting the mounted object. A vibration damping pad is included when appropriate. Variations of the clamp may be used in wall or parapet mount configurations.

Abstract: A method of specifying a configurable digital system is disclosed. According to the method, at least one design entity containing a functional portion of a digital system is specified in at least one hardware definition language (HDL) file. The design entity logically contains a configuration latch having a plurality of different possible configuration values that each corresponds to a different configuration of the functional portion of the digital system. A statement in the HDL file associates a Dial entity with the design entity. The Dial has a Dial input, a Dial output, and a mapping table indicating a mapping between each of a plurality of possible input values that can be received at the Dial input and a respective corresponding output value for the Dial output. The output value specifies which of the plurality of different possible configuration values is loaded into the configuration latch.

Abstract: A method and program product for instrumenting a hardware description language (HDL) design entity. The design entity is created utilizing a HDL source code file within the syntax convention of a platform HDL. In accordance with the method of the present invention an instrumentation entity is described within the HDL source code file utilizing a non-conventional syntax comment such that the instrumentation entity is embedded within the design entity without being incorporated into an overall design in which the design entity is incorporated. In accordance with a second embodiment, the HDL source code file includes a description of at least one operating event within the conventional syntax of the platform HDL, and the method of the present invention further includes associating the instrumentation entity with the operating event utilizing a non-conventional syntax comment within the HDL source code file.

Abstract: A configuration database associated with a hardware system stores at least one data structure defining a Dial instance and a mapping between each of a plurality of possible input values of the Dial instance and a respective one of a corresponding plurality of output values, where the plurality of output values controls which of a plurality of different possible latch values is placed in a hardware latch to configure the hardware system. The configuration database further indicates an association between the Dial instance and the hardware latch. In response to receipt of a request specifying an input value for the Dial instance, the configuration database is accessed to determine an output value for the Dial instance based upon the mapping. In addition, a latch value is obtained based upon the output value and the association. The latch value is then provided to the hardware system to set the hardware latch to the desired latch value.

Abstract: A configuration database associated with a hardware system stores at least one data structure defining a Dial instance and a mapping between each of a plurality of possible input values of the Dial instance and a respective one of a corresponding plurality of output values, where the plurality of output values controls which of a plurality of different possible latch values is placed in a hardware latch to configure the hardware system. The configuration database further indicates an association between the Dial instance and the hardware latch. In response to receipt of a request specifying an input value for the Dial instance, the configuration database is accessed to determine an output value for the Dial instance based upon the mapping. In addition, a latch value is obtained based upon the output value and the association. The latch value is then provided to the hardware system to set the hardware latch to the desired latch value.

Abstract: A configuration database associated with a digital design stores at least one data structure defining a Dial instance and a mapping between each possible input value of the Dial instance and a respective output value. The output value controls which of a number of different possible latch values is placed in a configuration latch to configure a functional portion of a simulation model of the digital design. The configuration database further indicates an association between the Dial instance and the configuration latch. In response to a request specifying an input value for the Dial instance, the data structure in the configuration database is accessed to determine an output value for the Dial instance based upon the mapping. In addition, a latch value for the configuration latch is obtained based upon the output value and the association indicated by the configuration database. The latch value is then utilized to set the configuration latch in the simulation model.

Abstract: A method for determining the configuration of a digital design first obtains a set of latch values of a plurality of latches within the digital design. A setting of a Dial instance is then determined based upon the set of latch values by reference to a configuration database that specifies a mapping table uniquely associating each a plurality of different settings of the Dial with a respective one of a plurality of different sets of latch values. The setting of the Dial instance is then output. In one embodiment, the setting of the Dial is contained in a simulation setup file utilized to configure a simulation model to a state approximating the state of the digital design represented by the set of latch values.

Abstract: A method of specifying a configurable digital system is disclosed. According to the method, at least one design entity containing a functional portion of a digital system is specified in at least one hardware definition language (HDL) file. The design entity logically contains a configuration latch having a plurality of different possible configuration values that each corresponds to a different configuration of the functional portion of the digital system. A statement in the HDL file associates a Dial entity with the design entity. The Dial has a Dial input, a Dial output, and a mapping table indicating a mapping between each of a plurality of possible input values that can be received at the Dial input and a respective corresponding output value for the Dial output. The output value specifies which of the plurality of different possible configuration values is loaded into the configuration latch.

Abstract: Border gateway protocol (BGP) tables and data flow statistics sorted by destination address are collected from a plurality of routers. The BGP tables and the data flow statistics are aggregated and correlated by a correlation node. The correlation node produces autonomous system (AS) transit volumes and AS terminating volumes by AS number. The AS transit volumes and the AS terminating volumes can be used to evaluate the suitability of transit providers and potential peers.

Abstract: A method and program product for instrumenting a hardware description language (HDL) design entity. The design entity is created utilizing a HDL source code file within the syntax convention of a platform HDL. In accordance with the method of the present invention an instrumentation entity is described within the HDL source code file utilizing a non-conventional syntax comment such that the instrumentation entity is embedded within the design entity without being incorporated into an overall design in which the design entity is incorporated. In accordance with a second embodiment, the HDL source code file includes a description of at least one operating event within the conventional syntax of the platform HDL, and the method of the present invention further includes associating the instrumentation entity with the operating event utilizing a non-conventional syntax comment within the HDL source code file.

Abstract: A cache memory provides a mechanism for storing and retrieving values wherein a hardware mechanism such as a partial address field selector is combined with an software generated selector in order to access specific congruence classes within a cache. Assignment of software generated selectors to specific types of data can be made in order to allow an operating system or application to efficiently manage cache usage.

Abstract: A partitioned cache and management method for selectively caching data by type improves the efficiency of a cache memory by partitioning congruence class sets for storage of particular data types such as operating system routines and data used by those routines. By placing values for associated applications into different partitions in the cache, values can be kept simultaneously available in cache with no interference that would cause deallocation of some values in favor of newly loaded values. Additionally, placing data from unrelated applications in the same partition can be performed to allow the cache to rollover values that are not needed simultaneously.

Abstract: A method and system are disclosed that utilize the expressiveness of hardware description languages for automatically adjusting counting rates of instrumentation within a simulation model of a digital circuit design, during simulation of said digital circuit design. According to the present invention a design entity that will be incorporated into a simulation model of a digital circuit design is described utilizing a hardware description language. The design entity operates, during simulation, in conformity with a design cycle that consists of a multiple of a simulator cycle. Next, an instrumentation entity is described utilizing the same hardware description language. The description of the instrumentation entity contains logic to detect occurrences of a count event that occurs in conformity with the design cycle during simulation.

Abstract: A method and system are disclosed that utilize the expressiveness of hardware description languages for providing comprehensive runtime monitoring during hardware accelerated simulation of a digital circuit design. According to the present invention a design entity forming part of a digital circuit design that will be translated and assembled into a simulation executable model, is described utilizing a hardware description language. Next, an instrumentation entity designed to send a failure signal in response to detecting an occurrence of a failure event within the simulation executable model is described utilizing the same hardware description language. Thereafter, a simulation test is initiated on the simulation executable model utilizing a hardware simulator. Finally, during the simulation test, and in response to receiving a failure signal from the instrumentation entity, the simulation test is terminated such that the failure event may be efficiently identified and diagnosed.