Patents by Inventor Ronald J. Bolam
Ronald J. Bolam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9310424Abstract: A mechanism is provided for determining a modeled age of a mufti-core processor. For each core in a set of cores in the multi-core processor, a determination is made of a temperature, a voltage, and a frequency at regular intervals for a set of degradations and a set of voltage domains, thereby forming the modeled age of the multi-core processor. A determination is made as to whether the modeled age of the multi-core processor is greater than an end-of-life value. Responsive to the modeled age of the multi-core processor being greater than an end-of-life value, an indication is sent that the multi-core processor requires replacement.Type: GrantFiled: February 25, 2013Date of Patent: April 12, 2016Assignee: International Business Machines CorporationInventors: Malcolm S. Allen-Ware, Ronald J. Bolam, Alan J. Drake, Charles R. Lefurgy, Barry P. Linder, Steven W. Mittl, Karthick Rajamani
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Publication number: 20140244212Abstract: A mechanism is provided for determining a modeled age of a mufti-core processor. For each core in a set of cores in the multi-core processor, a determination is made of a temperature, a voltage, and a frequency at regular intervals for a set of degradations and a set of voltage domains, thereby forming the modeled age of the multi-core processor. A determination is made as to whether the modeled age of the multi-core processor is greater than an end-of-life value. Responsive to the modeled age of the multi-core processor being greater than an end-of-life value, an indication is sent that the multi-core processor requires replacement.Type: ApplicationFiled: February 25, 2013Publication date: August 28, 2014Applicant: International Business Machines CorporationInventors: Malcolm S. Allen-Ware, Ronald J. Bolam, Alan J. Drake, Charles R. Lefurgy, Barry P. Linder, Steven W. Mittl, Karthick Rajamani
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Patent number: 8713490Abstract: A mechanism is provided for mitigating aging of a set of components in the data processing system. A modeled age of a component in the set of components is identified. A desired aging requirement for the component is identified and a determination is made as to whether the modeled age of the component is greater than the desired age of the component. Responsive to the modeled age of the component being greater than the desired age of the component, a policy is implemented to mitigate the aging of the component.Type: GrantFiled: February 25, 2013Date of Patent: April 29, 2014Assignee: International Business Machines CorporationInventors: Malcolm S. Allen-Ware, Ronald J. Bolam, Alan J. Drake, Charles R. Lefurgy, Barry P. Linder, Steven W. Mittl, Karthick Rajamani
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Patent number: 8227849Abstract: The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.Type: GrantFiled: February 17, 2010Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: Ebenezer E Eshun, Ronald J Bolam, Douglas D Coolbaugh, Keith E Downes, Natalie B Feilchenfeld, Zhong-Xiang He
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Patent number: 7890893Abstract: Disclosed is a design structure for a semiconductor chip structure that incorporates a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.Type: GrantFiled: March 19, 2008Date of Patent: February 15, 2011Assignee: International Business Machines CorporationInventors: Ronald J. Bolam, Tom C. Lee, Timothy D. Sullivan
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Patent number: 7838958Abstract: Disclosed are embodiments of a semiconductor chip structure and a method that incorporate a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.Type: GrantFiled: January 10, 2008Date of Patent: November 23, 2010Assignee: International Business Machines CorporationInventors: Ronald J. Bolam, Tom C. Lee, Timothy D. Sullivan
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Publication number: 20100149723Abstract: The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.Type: ApplicationFiled: February 17, 2010Publication date: June 17, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: EBENEZER E. ESHUN, RONALD J. BOLAM, DOUGLAS D. COOLBAUGH, KEITH E. DOWNES, NATALIE B. FEILCHENFELD, ZHONG-XIANG HE
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Patent number: 7728372Abstract: The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.Type: GrantFiled: May 10, 2006Date of Patent: June 1, 2010Assignee: International Business Machines CorporationInventors: Ebenezer E. Eshun, Ronald J. Bolam, Douglas D. Coolbaugh, Keith E. Downes, Natalie B. Feilchenfeld, Zhong-Xiang He
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Publication number: 20090179689Abstract: Disclosed are embodiments of a semiconductor chip structure and a method that incorporate a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.Type: ApplicationFiled: January 10, 2008Publication date: July 16, 2009Inventors: Ronald J. Bolam, Tom C. Lee, Timothy D. Sullivan
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Publication number: 20090183131Abstract: Disclosed is a design structure for a semiconductor chip structure that incorporates a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.Type: ApplicationFiled: March 19, 2008Publication date: July 16, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ronald J. Bolam, Tom C. Lee, Timothy D. Sullivan
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Patent number: 7541829Abstract: A method for correcting of asymmetric shifts in threshold voltage of transistors caused by effects such as negative-bias temperature instability (NBTI) during burn-in. The method may include providing logic patterns to an integrated circuit, such that devices that were stressed during burn-in are relaxed, and devices that suffered less stress during burn-in are stressed.Type: GrantFiled: June 2, 2008Date of Patent: June 2, 2009Assignee: International Business Machines CorporationInventors: Ronald J. Bolam, Terrance W. Kueper, David P. Paulsen, John E. Sheets, II
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Publication number: 20090063061Abstract: A circuit, method, and computer readable medium that enables on-chip monitoring of transistor degradation. The circuit includes an on-chip reference ring oscillator electrically coupled to an on-chip reference counter. An on-chip stressed ring oscillator is electrically coupled to an on-chip test counter. A test enable input is electrically coupled with the reference counter, the test counter, and the reference ring oscillator. When the test enable input is asserted the reference ring oscillator places a bit sequence proportional to the reference ring oscillator frequency on the reference counter simultaneously while the stressed ring oscillator places bit sequence proportional to the stressed ring oscillator frequency on the test counter. A difference in bit sequence between the reference counter and the test counter is compared to determine a relative difference there between.Type: ApplicationFiled: August 30, 2007Publication date: March 5, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: RONALD J. BOLAM, Keith A. Jenkins, Kevin G. Stawiasz
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Patent number: 7298161Abstract: A method and system for predicting gate reliability. The method comprises the steps of stressing a gate dielectric test site to obtain gate dielectric test site data and using the test site data to predict gate reliability. Preferably, the test structure and the product structure are integrated in such a manner that a test site occupies some of the product area and the product itself occupies the remainder of the product area.Type: GrantFiled: March 24, 2005Date of Patent: November 20, 2007Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Ronald J. Bolam, Edward J. Nowak, Alvin W. Strong, Jody J. Van Horn, Ernest Y. Wu
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Patent number: 6891359Abstract: A method and system for predicting gate reliability. The method comprises the steps of stressing a gate dielectric test site to obtain gate dielectric test site data and using the test site data to predict gate reliability. Preferably, the test structure and the product structure are integrated in such a manner that a test site occupies some of the product area and the product itself occupies the remainder of the product area.Type: GrantFiled: January 24, 2003Date of Patent: May 10, 2005Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Ronald J. Bolam, Edward J. Nowak, Alvin W. Strong, Jody J. Van Horn, Ernest Y. Wu
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Publication number: 20040145384Abstract: A method and system for predicting gate reliability. The method comprises the steps of stressing a gate dielectric test site to obtain gate dielectric test site data and using the test site data to predict gate reliability. Preferably, the test structure and the product structure are integrated in such a manner that a test site occupies some of the product area and the product itself occupies the remainder of the product area.Type: ApplicationFiled: January 24, 2003Publication date: July 29, 2004Applicant: International Business Machines CorporationInventors: Kerry Bernstein, Ronald J. Bolam, Edward J. Nowak, Alvin W. Strong, Jody J. Van Horn, Ernest Y. Wu
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Patent number: 6563173Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.Type: GrantFiled: May 16, 2001Date of Patent: May 13, 2003Assignee: International Business Machines CorporationInventors: Ronald J. Bolam, Subhash B. Kulkarni, Dominic J. Schepis
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Patent number: 6492684Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.Type: GrantFiled: June 11, 2001Date of Patent: December 10, 2002Assignee: International Business Machines CorporationInventors: Ronald J. Bolam, Subhash B. Kulkarni, Dominic J. Schepis
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Patent number: 6437594Abstract: A monitor for detecting pass gate leakage in a silicon on insulator device and a method for using the same is described herein. A pulse generator supplies a signal to a set of buffers connected in parallel, which pass on a signal to the source side of a series of NFETs. The plurality of NFETs are ordered by increasing channel widths. The NFETs have grounded gates, and therefore will not pass current due to field effects. Each NFET is connected to a latch, and the latches are originally set to the same state. When the signal supplied to the NFET drops from high to low, pass gate leakage will occur through the channel of each NFET. If pass gate leakage through any given NFET is sufficient, the latch will change states. The latch output signal is sent to a shift register, which can be made to output information. By incorporating the monitor on the chip, pass gate leakage tolerances and specifications can be established in-line during manufacture.Type: GrantFiled: March 17, 2000Date of Patent: August 20, 2002Assignee: International Business Machines CorporationInventors: Ronald J. Bolam, Andres Bryant, Edward J. Nowak, Minh H. Tong
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Publication number: 20020043686Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.Type: ApplicationFiled: June 11, 2001Publication date: April 18, 2002Inventors: Ronald J. Bolam, Subhash B. Kulkarni, Dominic J. Schepis
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Patent number: RE40339Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.Type: GrantFiled: December 3, 2004Date of Patent: May 27, 2008Assignee: International Business Machines CorporationInventors: Ronald J. Bolam, Subhash B. Kulkami, Dominic J. Schepis