Patents by Inventor Ronald J. C. Chwang

Ronald J. C. Chwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4613886
    Abstract: A CMOS static memory cell comprising a bistable circuit is described. A grounded p-type region separates the p-channel transistors of the circuit from the n-channel transistors. This p-type region reduces latch up problems and permits polysilicon lines to be routed over the region. The resultant memory cell is of higher density than prior art cells.
    Type: Grant
    Filed: December 13, 1985
    Date of Patent: September 23, 1986
    Assignee: Intel Corporation
    Inventor: Ronald J. C. Chwang
  • Patent number: 4409259
    Abstract: A high density CMOS dynamic RAM cell comprising a transistor and capacitance means formed in an n-well is disclosed. The capacitance means includes a polysilicon plate member disposed above a p-type region formed in the n-well. A buried contact, extending from the plate member, pierces the p-type region and contacts the well. In addition to the capacitance associated with the plate member, p-type region and well, capacitance is obtained between the side walls of the n-type regions and p-type regions.
    Type: Grant
    Filed: July 29, 1982
    Date of Patent: October 11, 1983
    Assignee: Intel Corporation
    Inventors: Mark T. Bohr, Kenneth K. Yu, Ronald J. C. Chwang, C. Neil Berglund
  • Patent number: 4364075
    Abstract: A high density CMOS dynamic RAM cell comprising a transistor and capacitance means formed in an n-well is disclosed. The capacitance means includes a polysilicon plate member disposed above a p-type region formed in the n-well. A buried contact, extending from the plate member, pierces the p-type region and contacts the well. In addition to the capacitance associated with the plate member, p-type region and well, capacitance is obtained between the side walls of the n-type regions and p-type regions.
    Type: Grant
    Filed: September 2, 1980
    Date of Patent: December 14, 1982
    Assignee: Intel Corporation
    Inventors: Mark T. Bohr, Kenneth K. Yu, Ronald J. C. Chwang, Neil C. Berglund