Abstract: In a computer system having a configuration which is subject to change, because of failure replacement, updating, or expansion, it is necessary to provide means for loading parameters carrying the present system configuration into the active modules of the system. In this manner, all parallel processors are identified and recognized and depending upon system demands, used because of the parameter loading arrangement of this computer system. Serial lines are provided for loading the parameters into the active modules.

Abstract: A controller has a node interface logic (40), a ring bus interface logic (42), a set of input pins (44) and a set of output pins (45). A common logic (58) is connected to the node interface logic (40) and to the ring bus interface logic (42). The common logic includes an output FIFO buffer (32) connected to an output link interface (37) and an input FIFO buffer (34) connected to an input link interface (36). A mode select pin (43) is provided for selecting a node controller mode of operation and a ring controller mode of operation. The node interface (40) responds to assertion of the selection pin (43) to activate the pins (44, 45) with respect to the node interface (40). The ring bus interface (42) responds to deassertion of the select pin (43) to activate the pins (44, 45) with respect to the ring bus interface (42).

Abstract: A star local area network includes a ring bus hub (4) capable of being connected to a plurality of nodes (3, 5, 9) geographically distant from the hub by means of low speed serial links (18, 19, 21, 28). The nodes include processor means (2, 30, 31) for creating messages for transfer on the network. A plurality of duplex communication links (18, 19, 21, 28) connect the nodes to the ring bus hub (4). The hub (40) is comprised of a plurality of ring controllers (10, 12, 14, 16) driven by a common clock source (7). Each ring controller is connected by means of a number of parallel lines to other ring controllers in series to form a closed ring. Each one (3) of the plurality of nodes is geographically distant from the hub (4) and is connected to a corresponding one (10) of the ring controllers by means of one (18, 19) of the duplex communication links. The node controllers including node interface means (40) for transmitting the messages as a contiguous stream of words on the duplex communication link.

Abstract: A data processor bus in which information is transferred between agents attached to the bus by issuing request packets that request data from an agent on the bus and reply packets that return data requested by a request packet. A control method mixes request-and-reply packets on the bus by determining the use of a next-bus cycle using arbitration, reply deferral, and specification lines and the state of a grant queue and a pipe queue in accordance with a specified protocol. A request is forced to take the next available bus cycle upon the condition that there is an agent identified in the great queue and the pipeline queue is not full. A reply packet is forced to take the next available bus cycle upon the condition that the pipeline queue is full. A reply packet is forced to take the next available bus cycle upon the condition that the grant queue is empty and the pipeline queue is not empty. Giving requests precedence over replies to allows the pipeline to be kept as full as possible.

Abstract: A ring hub in a local area network. A parallel ring bus (20, 22, 24, 26) connects a plurality of ring controllers (10, 12, 14, 16) in a closed loop. At reset time one controller (12) is selected to act as a ring monitor and is not connected to a network node. Each one of the remaining controllers are connected to a single node, so that one controller is linked to a corresponding node. The ring monitor and the ring controllers communicate by inserting message packets onto the bus and stripping messages and control information off of the bus. A transfer request packet is used by a source controller (10) to signal a destination controller (14) for permission to send a data packet. A packet acknowledge signal is generated at the destination controller (14) by asserting one of the bus control lines. The packet acknowledge signal is used to signal to the source controller that the transfer request packet has been received and placed in a request queue (40) at the destination controller.

Abstract: A link (19) connects a first controller (6) and a second controller (10) in a local area network. The second controller sends a header to the first controller (6) containing status information as to the status of an input buffer (70) at the second controller. The flow of the message data from a first buffer (44) at the first controller is controlled depending upon the status of the input buffer (70) at the second node. This prevents overflow of the input buffer (70) by controlling the rate at which new messages are placed on the transmit data link (19).

Abstract: Control logic for controlling references to a cache (24) including a cache directory (62) which is capable of being configured into a plurality of ways, each way including tag and valid-bit storage for associatively searching the directory (62) for cache data-array addresses. A cache-configuration register and control logic (64) splits the cache directory (62) into two logical directories, one directory for controlling requests from a first processor and the other directory for controlling requests from a second processor. A prefetch buffer (63) is provided along with a prefetch control register for splitting the prefetch buffer into two logical channels, a first channel for handling prefetches associated with requests from the first processor, and a second channel for handling prefetches associated with requests from the second processor.