Abstract: In some examples, an integrated circuit (IC) includes a semiconductor substrate defining a perimeter of the integrated circuit and a castellation formed at the perimeter. The IC also may include a layer including an electrically conductive material formed on a surface of the castellation. In some examples, the layer including the electrically conductive material is not substantially parallel to adjacent portions of the perimeter of the IC. The integrated circuit may be used in a system, in which the metallized castellation may be used to electrically connect the IC to an external structure, such as another IC or a printed board.

Abstract: Systems and methods for fabricating a multi-axis sensor are provided. In one implementation, a method comprises: fabricating a first die having a first active surface with first application electronics; fabricating a second die having a second active surface with second application electronics and a plurality of electrical connections that extend from the second application electronics to a side surface interface of the second die that is adjacent to the second active surface; aligning the side surface interface to be coplanar with the first active surface; and forming at least one electrical connection between the plurality of electrical connections and the first active surface.

Abstract: Systems and methods for fabricating a multi-axis sensor are provided. In one implementation, a method comprises: fabricating a first die having a first active surface with first application electronics; fabricating a second die having a second active surface with second application electronics and a plurality of electrical connections that extend from the second application electronics to a side surface interface of the second die that is adjacent to the second active surface; aligning the side surface interface to be coplanar with the first active surface; and forming at least one electrical connection between the plurality of electrical connections and the first active surface.

Abstract: A heater for heating packaged die for burn-in and heat testing is described. The heater may be a ceramic-type heater with a metal filament. The heater may be incorporated into the integrated circuit package as an additional ceramic layer of the package, or may be an external heater placed in contact with the package to heat the die. Many different types of integrated circuit packages may be accommodated. The method provides increased energy efficiency for heating the die while reducing temperature stresses on testing equipment. The method allows the use of multiple heaters to heat die to different temperatures. Faulty die may be heated to weaken die attach material to facilitate removal of the die. The heater filament or a separate temperature thermistor located in the package may be used to accurately measure die temperature.

Abstract: A method and system for stacking integrated circuits is described. An integrated circuit stack is formed by stacking integrated circuit pairs. The integrated circuit pairs are formed by connecting an active surface of a first integrated circuit to an active surface of a second integrated circuit using flip chip bonding. The first integrated circuit pair is connected to a substrate using an adhesive. The other integrated circuit pairs are stacked sequentially on the first integrated circuit pair using an adhesive. Wire bonding is used to connect the second integrated circuit in each of the integrated circuit pairs to the substrate.

Abstract: A design for stacking integrated circuits is described. Some integrated circuits have multiple signal pads that are common between a top integrated circuit and a bottom integrated circuit in an integrated circuit pair. These common pads are placed symmetrically on the integrated circuit. Unique signal pads are provided independently to each integrated circuit in a stack. An optional array of solder bumps placed over a central area of the integrated circuit may be used, which provides for heat transfer through the stack. When stacking multiple pairs of integrated circuits, the top integrated circuit in the integrated circuit stack pair serves as a spacer between the first and second pair of integrated circuits.

Abstract: A heater for heating packaged die for burn-in and heat testing is described. The heater may be a ceramic-type heater with a metal filament. The heater may be incorporated into the integrated circuit package as an additional ceramic layer of the package, or may be an external heater placed in contact with the package to heat the die. Many different types of integrated circuit packages may be accommodated. The method provides increased energy efficiency for heating the die while reducing temperature stresses on testing equipment. The method allows the use of multiple heaters to heat die to different temperatures. Faulty die may be heated to weaken die attach material to facilitate removal of the die. The heater filament or a separate temperature thermistor located in the package may be used to accurately measure die temperature.

Abstract: An IC package that employs top-side conduction cooling. The IC package has a low thermal resistance between a substrate housed within the package and the lid of the package. Thermal resistance is decreased by increasing the conduction cross-sections laterally through the package and lid and vertically from the package into the lid. The lid may also be modified with an extended mesa portion that reduces the gap between the lid and the IC. A thermally conductive spacer may also be interposed between the IC and the lid. Also, the package housing body and lid may be made from high thermal conductivity materials having thermal conductivities of 50 W/mK or greater with matching CTE between the lid and the package.

Abstract: An IC package that employs top-side conduction cooling. The IC package has a low thermal resistance between a substrate housed within the package and the lid of the package. Thermal resistance is decreased by increasing the conduction cross-sections laterally through the package and lid and vertically from the package into the lid. The lid may also be modified with an extended mesa portion that reduces the gap between the lid and the IC. A thermally conductive spacer may also be interposed between the IC and the lid. Also, the package housing body and lid may be made from high thermal conductivity materials having thermal conductivities of 50 W/mK or greater with matching CTE between the lid and the package.

Abstract: Methods and apparatus for vertical chip-on-board sensor packages can comprise a vertical sensor circuit component comprising a first face, a second face, a bottom edge, a top edge, two side edges, input/output (I/O) pads and at least one sensitive direction wherein the I/O pads are arranged near the bottom edge. Such vertical die chip-on-board sensor packages can also comprise one or more horizontal sensor circuit components comprising a top face, a printed circuit board (PCB) mounting face, a vertical sensor circuit component interface edge, two or more other edges, and one or more sensitive directions wherein the vertical sensor circuit component interface edge supports the vertical sensor circuit component along the Z axis and conductively or non-conductively connects to the vertical sensor circuit component.

Abstract: A ball grid array mounted circuit includes a stress relief substrate having spaced conductive vias extending between its surfaces and connection pads at the surfaces. Solder connections formed from solder balls connect between pads at the top surface and connection pads at an electronic component. Solder connections formed from solder balls connect between pads at the bottom surface and connection pads at a printed circuit board (PCB). The solder connections absorb at least a portion of the stress due to differences between the thermal coefficient of expansion of the electronic component and the PCB.

Abstract: A ball grid array mounted circuit includes a stress relief substrate having spaced conductive vias extending between its surfaces and connection pads at the surfaces. Solder connections formed from solder balls connect between pads at the top surface and connection pads at an electronic component. Solder connections formed from solder balls connect between pads at the bottom surface and connection pads at a printed circuit board (PCB). The solder connections absorb at least a portion of the stress due to differences between the thermal coefficient of expansion of the electronic component and the PCB.

Abstract: A method for performing an elevated temperature process on an integrated device whereby a magnetic field is used to maintain the alignment of magnetic domains in magnetically sensitive materials.

Abstract: Chip stacking and capacitor mounting arrangement including a planar spacer separating a first die and a second die. A conductive spacer provides for backside chip grounding in one application and provides for capacitor mounting in another application.

Abstract: A shielding apparatus for an electronic component includes a first insulative encapsulant surrounding at least a portion of the component and a second encapsulant surrounding said first encapsulant and having conductive particles dispersed therein for absorbing ionizing radiation.

Abstract: Bare die test device for making temporary electrical connections between bonding pads on the die and external test connectors includes a die chuck, a fanout substrate, and a substrate chuck. The fanout substrate has conductive bumps spaced for registration with die bonding pads. A die chuck receives the die and a substrate chuck holds the fanout substrate. In a fixed alignment embodiment, an alignment arrangement between the die chuck and the substrate chuck provides registration. In an alternative embodiment, the fanout substrate has a backside etched cavity exposing a transparent compliant material. A lower frame provides for lateral and angular positioning of the die chuck relative to the substrate chuck to bring the conductive bumps into alignment with the bonding pads, while visually observing the alignment through the transparent material.

Abstract: A constant energy, constant spark rate ignitor system suitable for use in high energy ignition systems. The ignitor system includes a vacuum interrupter switch through which an energy storage capacitor discharges to fire a surface gap spark plug. Discharge of the energy storage capacitor through the vacuum interrupter can only occur upon actuation of the switch. The quantity of energy stored in the energy storage capacitor and the timing of capacitor discharge is therefore not a function of ambient operating conditions or the dielectric properties of the switch and can therefore be independently controlled. A voltage comparator and spark rate clock are used to trigger closure of the vacuum interrupter switch and fire the plug when the capacitor contains the desired quantity of energy and a clock signal is present. A current proving circuit is also provided to verify that current passes through the spark plug.

Abstract: A system for manufacturing multiple component assemblies utilizing semi-automatic computer-assisted material handling. The system comprises a plurality of component selection cells each having an alphanumeric display to display a selected assembly model description and a plurality of component bins wherein each bin has an associated bin numeric display or backlight pushbutton switch for displaying the quantity of components from that bin required for a selected assembly model. Each numeric display pushbutton switch has a means for clearing the display after the required quantity of components has been selected and for generating a control signal in response to a completion of a selected collection of parts for that cell relating to the selected assembly model.

Abstract: A system for manufacturing multiple component assemblies utilizing semi-automatic computer-assisted material handling. The system comprises a plurality of component selection cells each having an alphanumeric display to display a selected assembly model description and a plurality of component bins wherein each bin has an associated numeric display for displaying the quantity of components from that bin required for a selected assembly model. Each numeric display has a means for clearing the display after the required quantity of components has been selected and for generating a control signal in response to a completion of a selected collection of parts for that cell relating to the selected assembly model. A computer controls the alphanumeric and numeric displays responsive to data entered by an operator relating to the selected assembly model number and controls the clearing of the alphanumeric displays in response to the control signal.