Patents by Inventor Ronald J. Molnar

Ronald J. Molnar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5672909
    Abstract: Two interdigitated comb-shaped fixed voltage buses such as a power bus and ground bus, in the form of metallization are provided substantially encircling of an integrated circuit die in an integrated circuit package or other integrated die assembly. Any selection of bonding pads on the die and metallization leads in the assembly may be connected to the fingers of either bus. The length of wire bond or TAB connections and the area occupied by the buses is minimized by the interdigitated geometry of the buses.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: September 30, 1997
    Assignee: Amkor Electronics, Inc.
    Inventors: Thomas P. Glenn, Ronald J. Molnar, Roy Dale Hollaway
  • Patent number: 5583378
    Abstract: A ball grid array package and low cost method for manufacture of the same is disclosed herein. The ball grid array package includes a thermal conductor which is a linearly co-extensive outer layer of an interconnection substrate and forms the outer surface of the ball grid array package. An integrated circuit chip is positioned on the underside of the package in a well region. The well region is either formed directly in the interconnection substrate or is formed by the application of a dam. The well region is then filled with an insulating encapsulant material to a predetermined level.
    Type: Grant
    Filed: May 16, 1994
    Date of Patent: December 10, 1996
    Assignee: Amkor Electronics, Inc.
    Inventors: Robert C. Marrs, Ronald J. Molnar
  • Patent number: 5138431
    Abstract: Where a lead frame or lead structure in a plastic or ceramic-type package is made of a ferromagnetic material, an electrically conducting non-ferromagnetic material is added to create a low-inductance path between a semiconductor die and the terminals of the package to reduce self-inductance in the package. To provide an effective low-inductance current path to the ferromagnetic lead frame, the cross-sectional dimensions of the non-ferromagnetic path is preferably no less than 50 microinches. Where the lead frame or lead structure is made from an electrically conducting non-ferromagnetic material, a ferromagnetic material is added to provide strength and rigidity to the lead frame or lead structure. The material added may be plated, spot plated, or cladded onto the starting material. The leads or terminals of a socket may be also be constructed in a similar manner to improve its wear-resistance and rigidity while maintaining a low self-inductance.
    Type: Grant
    Filed: January 31, 1990
    Date of Patent: August 11, 1992
    Assignee: VLSI Technology, Inc.
    Inventors: Chin-Ching Huang, Ronald J. Molnar