Abstract: A method for restoring an eroded portion in an exposed upper surface cavity of a metallic element in a microelectronic device, where the metallic element has a hardness, and the metallic element is laterally surrounded by lateral elements, where at least one structure within the lateral elements has a hardness that is greater than the hardness of the metallic element. A precursor material is deposited in at least the cavity of the upper surface of the metallic element. The precursor material is deposited to a thickness that at least fills the cavity of the upper surface of the metallic element. The precursor material has a hardness that is less than the hardness of the at least one structure within the lateral elements. The precursor material is removed as necessary from the lateral elements, and the precursor material is planarized. Only the precursor material within the cavity of the upper surface of the metallic element is selectively replaced with a desired material.

Abstract: A method for determining an end point of a planarization process for removing metal from a surface of a substrate submerged in an electrolytic solution or slurry. A first electrode is provided which is operable to contact the surface of the substrate, such as a working electrode of a potentiostat system. A second electrode is provided which is operable to contact the electrolytic solution, such as a reference electrode of the potentiostat system. The first electrode is contacted to the surface of the substrate and an electrochemical property is measured, such as the electrochemical potential between the first and second electrodes, where the electrochemical property is indicative of an electrochemical characteristic of the substrate-slurry system. The planarization process is preferably stopped when a substantial change in the electrochemical potential of the system is measured.

Abstract: A planarization process for an integrated circuit structure which inhibits or prevents cracking of low k dielectric material which comprises one of one or more layers of dielectric material formed over raised portions of the underlying integrated circuit structure. Prior to the planarization step, a removable mask is formed over such one or more dielectric layers formed over raised portions of the integrated circuit structure. Openings are formed in the mask to expose a portion of the upper surface of the one or more dielectric layers in the region over at least some of these raised portions of the integrated circuit structure. Exposed portions of the underlying one or more dielectric layers are then etched through such openings in the mask to reduce the overall amount of the one or more dielectric layers overlying such raised portions of the integrated circuit structure.

Abstract: A method for restoring an eroded portion in an exposed upper surface cavity of a metallic element in a microelectronic device, where the metallic element has a hardness, and the metallic element is laterally surrounded by lateral elements, where at least one structure within the lateral elements has a hardness that is greater than the hardness of the metallic element. A precursor material is deposited in at least the cavity of the upper surface of the metallic element. The precursor material is deposited to a thickness that at least fills the cavity of the upper surface of the metallic element. The precursor material has a hardness that is less than the hardness of the at least one structure within the lateral elements. The precursor material is removed as necessary from the lateral elements, and the precursor material is planarized. Only the precursor material within the cavity of the upper surface of the metallic element is selectively replaced with a desired material.

Abstract: A process is disclosed for planarizing a semiconductor substrate after filling isolation trenches in the substrate with dielectric material wherein the respective thicknesses of a liner layer of dielectric material blanket deposited over the upper surface of the substrate and in the trenches, and/or a filler layer of dielectric material blanket deposited over the liner layer to fill the trenches, may not be uniform.

Abstract: A method for restoring an eroded portion in an exposed upper surface cavity of a metallic element in a microelectronic device, where the metallic element has a hardness, and the metallic element is laterally surrounded by lateral elements, where at least one structure within the lateral elements has a hardness that is greater than the hardness of the metallic element. A precursor material is deposited in at least the cavity of the upper surface of the metallic element. The precursor material is deposited to a thickness that at least fills the cavity of the upper surface of the metallic element. The precursor material has a hardness that is less than the hardness of the at least one structure within the lateral elements. The precursor material is removed as necessary from the lateral elements, and the precursor material is planarized. Only the precursor material within the cavity of the upper surface of the metallic element is selectively replaced with a desired material.

Abstract: Methods and apparatus for planarizing the surface of a semiconductor wafer by applying non-uniform pressure distributions across the back side of the wafer are disclosed. According to one aspect of the present invention, a chemical mechanical polishing apparatus for polishing a first surface of a semiconductor wafer includes a polishing pad which polishes the first surface of the semiconductor wafer. The apparatus also includes a first mechanism which is used to hold, or otherwise support, the wafer during polishing, and a second mechanism that is used to apply a non-uniform pressure distribution through the first mechanism, directly onto a second surface of the wafer. The second mechanism is further used to facilitate polishing the first surface of the semiconductor wafer such that the first surface of the semiconductor wafer is evenly polished.

Abstract: A planarization process for an integrated circuit structure which inhibits or prevents cracking of low k dielectric material which comprises one of one or more layers of dielectric material formed over raised portions of the underlying integrated circuit structure. Prior to the planarization step, a removable mask is formed over such one or more dielectric layers formed over raised portions of the integrated circuit structure. Openings are formed in the mask to expose a portion of the upper surface of the one or more dielectric layers in the region over at least some of these raised portions of the integrated circuit structure. Exposed portions of the underlying one or more dielectric layers are then etched through such openings in the mask to reduce the overall amount of the one or more dielectric layers overlying such raised portions of the integrated circuit structure.

Abstract: The invention provides a process for selectively polishing a main electrically conductive layer of an integrated circuit structure by the steps of forming a polishing barrier layer over depressed regions of the main electrically conductive layer; and polishing the portion of the main electrically conductive layer not covered by the polishing barrier layer. The integrated circuit structure treated by the process of the invention contains one or more openings in a layer of dielectric material, and the main electrically conductive layer fills the one or more openings such that the depressed regions of the main electrically conductive layer overlie said one or more openings.

Abstract: A planarization process for an integrated circuit structure which inhibits or prevents cracking of low k dielectric material which comprises one of one or more layers of dielectric material formed over raised portions of the underlying integrated circuit structure. Prior to the planarization step, a removable mask is formed over such one or more dielectric layers formed over raised portions of the integrated circuit structure. Openings are formed in the mask to expose a portion of the upper surface of the one or more dielectric layers in the region over at least some of these raised portions of the integrated circuit structure. Exposed portions of the underlying one or more dielectric layers are then etched through such openings in the mask to reduce the overall amount of the one or more dielectric layers overlying such raised portions of the integrated circuit structure.

Abstract: A method for restoring an eroded portion in an exposed upper surface cavity of a metallic element in a microelectronic device, where the metallic element has a hardness, and the metallic element is laterally surrounded by lateral elements, where at least one structure within the lateral elements has a hardness that is greater than the hardness of the metallic element. A precursor material is deposited in at least the cavity of the upper surface of the metallic element. The precursor material is deposited to a thickness that at least fills the cavity of the upper surface of the metallic element. The precursor material has a hardness that is less than the hardness of the at least one structure within the lateral elements. The precursor material is removed as necessary from the lateral elements, and the precursor material is planarized. Only the precursor material within the cavity of the upper surface of the metallic element is selectively replaced with a desired material.

Abstract: A process for forming an integrated circuit structure wherein trenches and/or vias are formed in a predetermined pattern in a dielectric layer, lined with a barrier layer of a first electrically conductive material, and then filled with a second electrically conductive material, and the structure is then planarized to remove the first and second electrically conductive material from the upper surface of the dielectric layer, wherein the improvements comprise: a) before the planarizing step, forming over the second electrically conductive material a layer of a planarizable material capable of being planarized at about the same rate as the first electrically conductive material; and b) then planarizing the structure to remove: i) the planarizable material; ii) the second electrically conductive material; and iii) the first electrically conductive material; above the upper surface of the dielectric material; whereby the planarizable material above the second electrically conductive material in the trenche

Abstract: A method for planarizing an integrated circuit on a substrate to a target surface of the substrate where at least portions of the target surface are of a first material having a first reflectivity. The substrate is overlaid with a top layer of a second material having a second reflectivity thereby forming an upper surface. Material is removed from the upper surface in a planarizing process, and the first reflectivity and second reflectivity of the upper surface are sensed with multiple wavelengths of electromagnetic radiation. The planarization process is stopped when a ratio of the second reflectivity to the first reflectivity equals a predetermined value.

Abstract: Methods and apparatus for planarizing the surface of a semiconductor wafer by applying non-uniform pressure distributions across the back side of the wafer are disclosed. According to one aspect of the present invention, a chemical mechanical polishing apparatus for polishing a first surface of a semiconductor wafer includes a polishing pad which polishes the first surface of the semiconductor wafer. The apparatus also includes a first mechanism which is used to hold, or otherwise support, the wafer during polishing, and a second mechanism that is used to apply a non-uniform pressure distribution through the first mechanism, directly onto a second surface of the wafer. The second mechanism is further used to facilitate polishing the first surface of the semiconductor wafer such that the first surface of the semiconductor wafer is evenly polished.

Abstract: A polishing pad for chemical-mechanical polishing of an integrated circuit surface is described. The polishing pad includes a first polishing area having a first value of a physical property; and a second polishing area having a second value of said physical property, which said second value is different from the first value, such that during chemical-mechanical polishing of an integrated circuit surface, the integrated circuit rotates and oscillates on the polishing pad so that a substantial portion of the integrated circuit surface contacts both the first and second polishing areas, wherein a width of said first and second polishing areas is greater than about 40 mils.

Abstract: A process for modifying an alignment mark is described. The process includes: (i) fabricating the alignment mark on an integrated circuit substrate surface, which alignment mark includes an alignment mark fill material of defined composition; and (ii) introducing a step in the alignment mark by polishing the integrated circuit substrate surface and removing at least some of the alignment mark fill material from the integrated circuit substrate to form a modified alignment mark. The modified alignment mark is capable of allowing an alignment tool to detect the modified alignment mark when the modified alignment mark is covered by an opaque layer and thereby align a first layer of the integrated circuit substrate to the opaque layer that is disposed above the first layer.

Abstract: An end effector to facilitate conditioning a surface of a polishing pad used in chemical-mechanical polishing of a substrate surface is described. The end effector includes an inwardly recessing contact surface capable of attaching to a conditioning disk having a conditioning surface such that the conditioning surface conforms to a substantial portion of the polishing pad, which protrudes outwardly under operation and thereby effectively conditions a substantial portion of the polishing pad. The present invention also describes a conditioning disk for effectively conditioning a surface of a polishing pad used in chemical-mechanical polishing of a substrate surface. The conditioning disk includes (i) a second surface capable of attaching to a contact surface of an end effector and (ii) an inwardly recessing conditioning surface that conforms to a substantial portion of said polishing pad, which protrudes outwardly under operation, and thereby effectively conditions the polishing pad.

Abstract: A substrate holder assembly for forming a substantially uniformly polished substrate surface during chemical-mechanical polishing is described. The substrate holder assembly includes a carrier film having: (A) a porous layer with (i) a first surface with an outwardly protruding dome shaped region that applies pressure on at least a portion of the substrate surface during chemical-mechanical polishing and a location of the protruding dome shape is aligned with a location of an area of substrate surface that is likely to be underpolished, (ii) a second surface facing a contact surface of a backing plate; and (B) a pressure sensitive adhesive backing layer for affixing the carrier film to the contact surface of the backing plate under sufficient pressure.

Abstract: A process for compensating for degradation of a first polishing pad during polishing on the first polishing pad of a plurality of substrate surfaces that have substantially similar film stacks is described. The process includes: (a) characterizing a test polishing pad, which characterization includes determining changes in film removal rates of layers of the film stack during polishing of the plurality of the substrate surfaces on the test polishing pad; (b) polishing a first substrate surface on the first polishing pad, which is substantially similar to the test polishing pad, under a first set of polishing conditions; and (c) polishing a second substrate surface on the first polishing pad under a second set of polishing conditions. A difference between the second set of polishing conditions and the first set of polishing conditions is designed to minimize the changes in the film removal rates of the layers of the film stack and thereby compensate for degradation of the first polishing pad.

Abstract: A substrate holder assembly for retaining a substrate during chemical mechanical polishing is described. The substrate holder assembly includes: (i) a backing plate including a contact surface adapted for supporting components of the substrate holder assembly and the substrate; (ii) a shim positioned adjacent the contact surface of the backing plate for applying pressure on the substrate during chemical-mechanical polishing; and (iii) a carrier film disposed adjacent the shim such that at least a portion of the carrier film adjacent the shim protrudes outwardly.