Abstract: A method and apparatus for testing a semiconductor chip includes providing the semiconductor chip with a common input/output (I/O) or bidirectional I/O pad. The I/O pad is electrically coupled to an off-chip driver (OCD) and an off-chip receiver (OCR). The OCD, I/O pad, and OCR are combined in a common input/output (CIO) or bidirectional I/O configuration. The I/O pad is effectively open circuited by an external tester and a performance parameter of the IO circuits connected to the open circuited pad is tested.

Abstract: A built-in self-test (BIST) apparatus and method for testing an integrated circuit are disclosed which enable capture of failure data for a selected failure. The BIST apparatus comprises a clock generator, which generates at least a first clock signal, and a built-in self-tester, which applies predetermined input data patterns to the integrated circuit in response to the first clock signal. In addition, the BIST apparatus includes a data comparator for comparing output data received from the integrated circuit with expected output data. The data comparator detects a failure within the integrated circuit when the output data received from the integrated circuit differs from the expected output data. The BIST apparatus further includes a clock controller that disables the first clock signal in response to the detection of a selected occurrence of a failure.

Abstract: A printed circuit board especially for use in device testing apparatus is provided. The circuit board includes a plurality of stacked layers of dielectric or insulating material with each of the layers having coated on one surface thereof a layer of conducting material defining a plane. The conducting material extends to at least one outer edge of the stack of the material for each plane and at each plane it is spaced with respect to the outer edge locations of all of the other planes. A plurality of lands extend vertically along the stack of material, each land while extending the entire length, only contacting the plane of conducting material extending to the edge at the location of the land whereby a signal applied to any given land is conducted only on the planes where that plane extends to the surface.

Abstract: A memory array device with an embedded self-test binary pattern. The device has an array of bistable cells formed with first and second sides that are oppositely connected to a first voltage line or a second voltage line. If the first and second voltage lines are energized at the same voltage level, each of the bistable cells will function in a normal bistable mode. If the first and second voltage lines are energized at different levels, each of the bistable cells will function in an embedded binary pattern mode.

Abstract: A tester for logic circuits provided with a fast recovery power supply for supplying high current to a logic circuit under test and for measuring a low current of the circuit under test. The power supply of the tester has first and second amplifiers coupled to the CMOS circuit being tested and having dual feedback loops with one loop controlling the resistance of the other loop. The first amplifier is coupled between a reference voltage and a capacitor supplying current to the CMOS circuit under test. The second amplifier is coupled between the same reference voltage, and the output of the first amplifier. A resistive feedback is coupled between the circuit under test and the output of the first amplifier and an AC coupled impedance switching means is coupled between the output of the second amplifier and across the resistive feedback whereby the impedance switch can alter the impedance of the resistive feedback by shunting the resistor to recharge the capacitor supplying current to the circuit under test.