Abstract: A method of forming an integrated barrier/contact for stacked capacitors is provided which results in reduced cost of ownership and in a barrier which is nominally several times thicker than convention structures. The resulting structure results in decreased contact plug resistance as compared with conventional devices.

Abstract: The invention provides slurry-less chemical-mechanical polishing processes which are effective in planarizing oxide materials, especially siliceous oxides, even where the starting oxide layer has significant topographical variation. The processes of the invention are characterized by the use of a fixed abrasive polishing element and by use of an aqueous liquid medium containing a cationic surfactant for at least a portion of the polishing process involving reduction in the amount of topographic variation (height differential) across the oxide material on the substrate. The method reduces or eliminates the transfer of topographic variations to levels below the desired planarization level.

Abstract: An aqueous slurry-less composition for chemical-mechanical-polishing of a silicon dioxide workpiece comprising: a cationic surfactant that is soluble and ionized at neutral to alkaline pH conditions, in which the cationic surfactant is present in an aqueous slurry-less composition in an amount less than its critical micelle concentration.

Abstract: A semiconductor structure comprising a semiconductor substrate, an electrically conductive level on the substrate and a metal fuse located at the conductive level wherein the fuse comprises a self-aligned dielectric etch stop layer thereon is provided along with processes for its fabrication.

Abstract: Stress induced grain boundary movement in aluminum lines used as connections in integrated circuits is substantially avoided by doping the aluminum with iron. Through this expedient not only is grain boundary movement avoided but electromigration problems are also decreased.

Abstract: In some circuitry, field effect transistors are produced by employing polycrystalline conductive regions including the channel and connections to the source and drain. Conventional methods for producing such transistors involve depositing a thin polycrystalline channel region, patterning this region overlying the patterned region with an insulator, producing openings in the insulator for contacts to source and drain, and depositing a thick polycrystalline contact region. Processing complexity is, however, substantially reduced by first forming interconnect areas, source region and drain regions; then opening a region for the channel; and finally depositing a layer to form the channel. Thus, at least three processing steps are eliminated and vertical dimensions are reduced.

Abstract: For integrated circuit devices with strict design rules, junctions defining the source and drain are typically more shallow than 0.25 .mu.m and are made through vias having an aspect ratio greater than 1.1. Suitable electrical contact to such a shallow junction is quite difficult. To ensure an appropriate contact, an adhesion barrier layer such as titanium nitride or an alloy of titanium and tungsten is first deposited. Tungsten is then deposited under conditions which produce a self-limiting effect in a prototypical deposition on silicon. Additionally, these tungsten deposition conditions are adjusted to higher rather than lower deposition temperatures. Subsequent deposition of aluminum if desired, completes the contact.

Abstract: Disclosed is a method for manufacturing an integrated circuit which includes the step of evaluating the reliability of metal films in the circuit using a noise measurement technique. In one embodiment, a film portion to be tested is incorporated in a Wheatstone bridge. A relatively large direct current is passed through the film to stimulate 1/f.sup.2 noise. A relatively small alternating current is concurrently passed through the film. The bridge imbalance signal at the ac frequency is amplified and demodulated by a phase-locked amplifier, and is then frequency analyzed. The film is evaluated by comparing the resulting noise power spectrum with predetermined standards.

Abstract: Direct contact to shallow junctions in integrated circuits and interconnection between these contacts is achievable by utilizing a specific aluminum CVD process. In this process the aluminum is deposited utilizing a triisobutyl aluminum precursor onto a substrate having a nucleation layer, e.g. a titanium nitride layer. By appropriate choice of this nucleation layer to control the nucleation of the depositing aluminum, suitable contact is made while avoiding void defects present in the absence of such layer.

Abstract: Smoothing irregularities in a surface is accomplished by a wet-etchback technique. In this technique, a polysilicate composition is formed on a nonplanar substrate such as the surface of an integrated-circuit wafer. The polysilicate is etched away and the etching is continued into the underlying surface. As a result, a substantial smoothing of the surface is obtained.

Abstract: Stress induced grain boundary movement in aluminum lines used as connections in integrated circuits is substantially avoided by doping the aluminum with iron. Through this expedient not only is grain boundary movemenmt avoided but electromigration problems are also decreased.

Abstract: By adjusting the AC field conditions, i.e., by grounding the environment of a substrate being etched with a chlorine-containing plasma, a significant increase in etch selectivity is achieved. By applying a similar AC field adjustment to the reaction chamber surfaces, excellent etch uniformity is achieved in conjunction with excellent selectivity.

Abstract: The presence of material deposited on the sidewall during device fabrication utilizing plasma-effected etching of semiconductor materials has significant consequences in the properties of these devices. It has been found that such depositions lead to a sidewall slope that, among other things, in turn produces linewidth loss. Additionally, the presence of a sloped masking material, e.g., a photoresist or sidewall deposit, produces further undesirable results.

Abstract: The invention involves new etch monitoring and thickness measurement techniques which are more accurate than previous techniques. In accordance with the invention, the etch depth of a substrate region undergoing etching is monitored, or the thickness of the region is measured, by impinging the region with light and detecting the intensity of the reflected light. In contrast to the previous techniques, the incident light is chosen so that a substrate region underlying, and/or a patterned substrate region overlying the substrate region of interest is substantially opaque to the incident light, which precludes the formation of signals unrelated to etch depth or thickness.