Patents by Inventor Ronald James Jensen

Ronald James Jensen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8362607
    Abstract: An integrated circuit package includes a thermally and electrically conductive package lid. The package lid may be in electrical communication with an electrically conductive pad connected to a power plane, ground plane, or signal route in the integrated circuit. The electrically conductive package lid may provide an electrical connection for electrical power or electrical signals or may serve as an electrical ground. In some embodiments, the package lid may include a thermally and electrically conductive material. In other embodiments, the package lid may include an electrically insulative substrate coated on at least one surface with a layer of metal or another conductive material. The conductive layer may be electrically connected to electrical ground, a reference voltage, or a signal pay by at least one electrically conductive via.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: January 29, 2013
    Assignee: Honeywell International Inc.
    Inventors: David Scheid, Ronald James Jensen
  • Patent number: 8354743
    Abstract: An integrated circuit package base includes a plurality of tiers. In some examples, an integrated circuit package encloses a plurality of stacked integrated circuits that are each electrically coupled to an electrical contact located on a respective tier of the package base. The tiers of the integrated circuit package can have different elevations relative to a bottom surface of the integrated circuit package.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: January 15, 2013
    Assignee: Honeywell International Inc.
    Inventors: Ronald James Jensen, David Scheid
  • Publication number: 20110180919
    Abstract: An integrated circuit package base includes a plurality of tiers. In some examples, an integrated circuit package encloses a plurality of stacked integrated circuits that are each electrically coupled to an electrical contact located on a respective tier of the package base. The tiers of the integrated circuit package can have different elevations relative to a bottom surface of the integrated circuit package.
    Type: Application
    Filed: January 27, 2010
    Publication date: July 28, 2011
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Ronald James Jensen, David Scheid
  • Patent number: 7868362
    Abstract: A hypersensitive semiconductor die structure is disclosed, in which flip-chip packaging is used in conjunction with a modified SOI die in which a thick silicon support substrate has been removed to increase sensitivity of the sensing device. Rather than being located beneath layers of interconnects and dielectric, the disclosed structure places the sensing devices close to the surface, more closely exposed to the environment in which sensing is to occur. The structure also allows for the placement of sensing films on nearer to the sensing devices and/or an oxide layer overlying the sensing devices.
    Type: Grant
    Filed: October 16, 2008
    Date of Patent: January 11, 2011
    Assignee: Honeywell International Inc.
    Inventors: Todd Andrew Randazzo, Ronald James Jensen, Thomas Keyser
  • Publication number: 20100308453
    Abstract: An integrated circuit package includes a thermally and electrically conductive package lid. The package lid may be in electrical communication with an electrically conductive pad connected to a power plane, ground plane, or signal route in the integrated circuit. The electrically conductive package lid may provide an electrical connection for electrical power or electrical signals or may serve as an electrical ground. In some embodiments, the package lid may include a thermally and electrically conductive material. In other embodiments, the package lid may include an electrically insulative substrate coated on at least one surface with a layer of metal or another conductive material. The conductive layer may be electrically connected to electrical ground, a reference voltage, or a signal pay by at least one electrically conductive via.
    Type: Application
    Filed: June 3, 2009
    Publication date: December 9, 2010
    Applicant: Honeywell International Inc.
    Inventors: David Scheid, Ronald James Jensen
  • Publication number: 20090096113
    Abstract: A hypersensitive semiconductor die structure is disclosed, in which flip-chip packaging is used in conjunction with a modified SOI die in which a thick silicon support substrate has been removed to increase sensitivity of the sensing device. Rather than being located beneath layers of interconnects and dielectric, the disclosed structure places the sensing devices close to the surface, more closely exposed to the environment in which sensing is to occur. The structure also allows for the placement of sensing films on nearer to the sensing devices and/or an oxide layer overlying the sensing devices.
    Type: Application
    Filed: October 16, 2008
    Publication date: April 16, 2009
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Todd Andrew Randazzo, Ronald James Jensen, Thomas Keyser