Abstract: A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode.

Abstract: A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode.

Abstract: A memory device comprises a memory array and error correction circuitry coupled to the memory array. The error correction circuitry is configured to identify, in a data word retrieved from the memory array, at least one bit position corresponding to a predetermined defect location in the memory array, and to generate a corrected data word by automatically inverting a logic value at the identified bit position. This automatic logic inversion approach is particularly well suited for use in correcting output data errors associated with via defects and weak bit defects in high-density ROM devices.

Abstract: A memory device comprises a memory array and a phase distribution circuit coupled to the memory array. In one aspect, the phase distribution circuit is operative to control respective durations of a precharge phase and an active phase of a memory cycle of the memory array based on relative transistor characteristics of a tracked precharge transistor of a first conductivity type and a tracked memory cell transistor of a second conductivity type different than the first conductivity type. For example, the phase distribution circuit may comprise a first tracking transistor of the first conductivity type for tracking the precharge transistor of the first conductivity type and a second tracking transistor of the second conductivity type for tracking the memory cell transistor of the second conductivity type. The relative transistor characteristics may comprise relative strengths of the tracked precharge and memory cell transistors.

Abstract: A memory device comprises a memory array and a phase distribution circuit coupled to the memory array. In one aspect, the phase distribution circuit is operative to control respective durations of a precharge phase and an active phase of a memory cycle of the memory array based on relative transistor characteristics of a tracked precharge transistor of a first conductivity type and a tracked memory cell transistor of a second conductivity type different than the first conductivity type. For example, the phase distribution circuit may comprise a first tracking transistor of the first conductivity type for tracking the precharge transistor of the first conductivity type and a second tracking transistor of the second conductivity type for tracking the memory cell transistor of the second conductivity type. The relative transistor characteristics may comprise relative strengths of the tracked precharge and memory cell transistors.

Abstract: A memory circuit includes a plurality of memory cells and a plurality of bit lines and row lines connected to the memory cells for accessing selected memory cells. The memory circuit includes a programmable voltage source adapted for connection to at least one bit line and operative to precharge the bit line to a prescribed voltage level prior to accessing a selected one of the memory cells coupled to the bit line. A control circuit coupled to the bit line is operative to oppose discharge of the bit line during at least a portion of a given memory read cycle. A tracking circuit connected to the control circuit is operative to control a delay in activation of the control circuit and/or a duration of time the control circuit is active as a function of a parameter affecting signal development time of a data signal on the bit line.

Abstract: A memory device comprises a memory array, at least one buffer coupled to the memory array, and test circuitry coupled to the buffer. The buffer comprises switching circuitry configured to multiplex first and second inputs of the buffer to a given output of the buffer based at least in part on a control signal generated by the test circuitry. The control signal is generated as a function of both a test signal indicative of a test mode of operation of the memory device and a power-down signal indicative of a power-down mode of operation of the memory device. The buffer further comprises current reduction circuitry responsive to the control signal for reducing an amount of current consumed by the buffer in the power-down mode of operation. The buffer may comprise an input data buffer or an address buffer of the memory device.

Abstract: A sense amplifier includes a first sensing element and a second sensing element redundant to the first sensing element. The sense amplifier further comprises a switch circuit configured to switch between the first and second sensing elements when an offset of the sense amplifier is greater than a prescribed amount.

Abstract: A memory circuit having reduced power consumption includes a plurality of memory sub-arrays and a shared circuit coupled to each of the memory sub-arrays. Each memory sub-array includes at least one row circuit, at least one column circuit, and a plurality of memory cells operatively coupled to the row and column circuits. The row and column circuits are operative to provide selective access to one or more of the memory cells. The shared circuit includes circuitry, external to the memory sub-arrays, which is operative to control one or more functions of the memory sub-arrays as a function of at least one control signal supplied to the memory circuit. The memory circuit is operative, with at least one of the memory sub-arrays operative, with one or more of the memory sub-arrays powered and concurrently with one or more of the memory sub-arrays unpowered.

Abstract: A word line driver circuit for use in a memory array including multiple memory cells and multiple word lines coupled to the memory cells for selectively accessing the memory cells includes a driver adapted to generate a word line signal as a function of a first set of address signals received by the word line driver circuit. The circuit further includes a switching circuit having a plurality of output nodes, the output nodes connected to respective ones of the plurality of word lines, and having an input node connected to an output of the driver and adapted to receive the word line signal. The switching circuit is operative to direct the word line signal to a selected one of the word lines during a memory access as a function of at least one control signal. Between a given pair of memory accesses, the output nodes and the input node of the switching circuit are held to a same prescribed voltage level to thereby substantially eliminate a leakage current path in the switching circuit.

Abstract: A memory circuit includes a plurality of memory cells and a plurality of bit lines and row lines connected to the memory cells for accessing selected memory cells. The memory circuit includes a programmable voltage source adapted for connection to at least one bit line and operative to precharge the bit line to a prescribed voltage level prior to accessing a selected one of the memory cells coupled to the bit line. A control circuit coupled to the bit line is operative to oppose discharge of the bit line during at least a portion of a given memory read cycle. A tracking circuit connected to the control circuit is operative to control a delay in activation of the control circuit and/or a duration of time the control circuit is active as a function of a parameter affecting signal development time of a data signal on the bit line.

Abstract: A memory device comprises a memory array, at least one buffer coupled to the memory array, and test circuitry coupled to the buffer. The buffer comprises switching circuitry configured to multiplex first and second inputs of the buffer to a given output of the buffer based at least in part on a control signal generated by the test circuitry. The control signal is generated as a function of both a test signal indicative of a test mode of operation of the memory device and a power-down signal indicative of a power-down mode of operation of the memory device. The buffer further comprises current reduction circuitry responsive to the control signal for reducing an amount of current consumed by the buffer in the power-down mode of operation. The buffer may comprise an input data buffer or an address buffer of the memory device.

Abstract: A word line driver circuit for use in a memory array including multiple memory cells and multiple word lines coupled to the memory cells for selectively accessing the memory cells includes a driver adapted to generate a word line signal as a function of a first set of address signals received by the word line driver circuit. The circuit further includes a switching circuit having a plurality of output nodes, the output nodes connected to respective ones of the plurality of word lines, and having an input node connected to an output of the driver and adapted to receive the word line signal. The switching circuit is operative to direct the word line signal to a selected one of the word lines during a memory access as a function of at least one control signal. Between a given pair of memory accesses, the output nodes and the input node of the switching circuit are held to a same prescribed voltage level to thereby substantially eliminate a leakage current path in the switching circuit.

Abstract: A sense amplifier includes a first sensing element and a second sensing element redundant to the first sensing element. The sense amplifier further comprises a switch circuit configured to switch between the first and second sensing elements when an offset of the sense amplifier is greater than a prescribed amount.

Abstract: A memory circuit having reduced power consumption includes a plurality of memory sub-arrays and a shared circuit coupled to each of the memory sub-arrays. Each memory sub-array includes at least one row circuit, at least one column circuit, and a plurality of memory cells operatively coupled to the row and column circuits. The row and column circuits are operative to provide selective access to one or more of the memory cells. The shared circuit includes circuitry, external to the memory sub-arrays, which is operative to control one or more functions of the memory sub-arrays as a function of at least one control signal supplied to the memory circuit. The memory circuit is operative, with at least one of the memory sub-arrays operative, with one or more of the memory sub-arrays powered and concurrently with one or more of the memory sub-arrays unpowered.

Abstract: A row line driver circuit for use in a memory array including multiple memory cells and multiple row lines coupled to the memory cells for selectively accessing the memory cells includes an output stage adapted for connection to a corresponding one of the row lines and a control circuit connected to the output stage. The output stage is operative during an active phase of a given memory cycle to drive the corresponding row line to a potential as a function of at least one address signal received by the driver circuit. The control circuit is operative to generate at least one control signal for disabling the output stage at least during an inactive phase of the memory cycle to thereby substantially eliminate a leakage current path in the driver circuit.

Abstract: A memory cell for use in a content-addressable memory comprises a first latch and a second latch. The first latch is operative to store a first bit associated with a first stored word, while the second latch is operative to store a second bit associated with a second stored word. The first and second latches collectively comprise a plurality of latch transistors. Each of the latch transistors comprises a respective channel. The channels of the latch transistors are oriented in substantially the same direction, resulting in a very compact memory cell implementation.

Abstract: A row line driver circuit for use in a memory array including multiple memory cells and multiple row lines coupled to the memory cells for selectively accessing the memory cells includes an output stage adapted for connection to a corresponding one of the row lines and a control circuit connected to the output stage. The output stage is operative during an active phase of a given memory cycle to drive the corresponding row line to a potential as a function of at least one address signal received by the driver circuit. The control circuit is operative to generate at least one control signal for disabling the output stage at least during an inactive phase of the memory cycle to thereby substantially eliminate a leakage current path in the driver circuit.

Abstract: A memory cell for use in a content-addressable memory comprises a first latch and a second latch. The first latch is operative to store a first bit associated with a first stored word, while the second latch is operative to store a second bit associated with a second stored word. The first and second latches collectively comprise a plurality of latch transistors. Each of the latch transistors comprises a respective channel. The channels of the latch transistors are oriented in substantially the same direction, resulting in a very compact memory cell implementation.

Abstract: A memory device comprises a memory array and error correction circuitry coupled to the memory array. The error correction circuitry is configured to identify, in a data word retrieved from the memory array, at least one bit position corresponding to a predetermined defect location in the memory array, and to generate a corrected data word by automatically inverting a logic value at the identified bit position. This automatic logic inversion approach is particularly well suited for use in correcting output data errors associated with via defects and weak bit defects in high-density ROM devices.