Patents by Inventor Ronald Jay V. Peralta

Ronald Jay V. Peralta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Die attach pick error detection
    Patent number: 10388609
    Abstract: Embodiments of the invention provide a method to detect pick and place indexing errors on each manufacturing batch (lot) of semiconductor wafer processed during a die attach process using a preselected skeleton of check die. The known locations of the check skeleton die are verified during picking of die from the wafer. If the check skeleton cannot be correctly verified at the known locations, then a pick error is indicated. The embodiments may be implemented on existing die attach equipment.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: August 20, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dale Ohmart, Balamurugan Subramanian, Renato Heracleo Orduna Leano, Sonny Evangelista Dipasupil, Ronald Jay V. Peralta
  • WAFER WITH DIE MAP
    Publication number: 20160141251
    Abstract: Embodiments of the invention provide a semiconductor wafer with information for detecting a die attach pick error on the semiconductor wafer. The semiconductor wafer has a plurality of electrical chips. The semiconductor wafer also has a die map with a plurality of locations of a set of pre-selected check good electrical chips (CGEC) die from the plurality of electrical chips on the semiconductor wafer and flat edge orientation marker. A reference feature located in a predetermined area of the semiconductor wafer. A reference die is located in a known spatial relationship to the reference feature. The die map is defined relative to the location of the reference die on the semiconductor wafer.
    Type: Application
    Filed: November 25, 2015
    Publication date: May 19, 2016
    Inventors: Dale Ohmart, Balamurugan Subramanian, Renato Heracleo Orduna Leano, Sonny Evangelista Dipasupil, Ronald Jay V. Peralta
  • Die attach pick error detection
    Patent number: 9229058
    Abstract: Embodiments of the invention provide a method to detect pick and place indexing errors on each manufacturing batch (lot) of semiconductor wafer processed during a die attach process using a preselected skeleton of check die. The known locations of the check skeleton die are verified during picking of die from the wafer. If the check skeleton cannot be correctly verified at the known locations, then a pick error is indicated. The embodiments may be implemented on existing die attach equipment.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: January 5, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dale Ohmart, Balamurugan Subramanian, Renato Heracleo Orduna Leano, Sonny Evangelista Dipasupil, Ronald Jay V. Peralta
  • Die Attach Pick Error Detection
    Publication number: 20140002128
    Abstract: Embodiments of the invention provide a method to detect pick and place indexing errors on each manufacturing batch (lot) of semiconductor wafer processed during a die attach process using a preselected skeleton of check die. The known locations of the check skeleton die are verified during picking of die from the wafer. If the check skeleton cannot be correctly verified at the known locations, then a pick error is indicated. The embodiments may be implemented on existing die attach equipment.
    Type: Application
    Filed: June 25, 2013
    Publication date: January 2, 2014
    Inventors: Dale Ohmart, Balamurugan Subramanian, Renato Heracleo Orduna Leano, Sonny Evangelista Dipasupil, Ronald Jay V. Peralta