Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel. Sidewall spacers are formed on side walls of the elongated gates. Portions of the elongated fins located between the elongated gates are removed, along with the underlying insulation, to expose the underlying substrate. One or more semiconductor material layers are then epitaxially grown from the underlying substrate at locations between the elongated gates. The one or more semiconductor material layers may include an undoped epi-layer and an overlying doped epi-layer. The epitaxial material defines a source or drain of the transistor.

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer (of either SOI or bulk type). Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers. A protective material is provided to cover the underlying substrate layer and define sidewall spacers on side walls of the elongated fins between the elongated gates. The first semiconductor material and insulating material of the elongated fins located between the protective material sidewall spacers (but not under the elongated gates) is removed to form trenches aligned with the channel regions. Additional semiconductor material is then epitaxially grown inside each trench between the elongated gates to form source-drain regions adjacent the channel regions formed by the elongated fins of the first semiconductor material located under the elongated gates.

Abstract: A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel. Sidewall spacers are formed on side walls of the elongated gates. Portions of the elongated fins located between the elongated gates are removed, along with the underlying insulation, to expose the underlying substrate. One or more semiconductor material layers are then epitaxially grown from the underlying substrate at locations between the elongated gates. The one or more semiconductor material layers may include an undoped epi-layer and an overlying doped epi-layer. The epitaxial material defines a source or drain of the transistor.

Abstract: A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel. Sidewall spacers are formed on side walls of the elongated gates. Portions of the elongated fins located between the elongated gates are removed, along with the underlying insulation, to expose the underlying substrate. One or more semiconductor material layers are then epitaxially grown from the underlying substrate at locations between the elongated gates. The one or more semiconductor material layers may include an undoped epi-layer and an overlying doped epi-layer. The epitaxial material defines a source or drain of the transistor.

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer (of either SOI or bulk type). Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers. A protective material is provided to cover the underlying substrate layer and define sidewall spacers on side walls of the elongated fins between the elongated gates. The first semiconductor material and insulating material of the elongated fins located between the protective material sidewall spacers (but not under the elongated gates) is removed to form trenches aligned with the channel regions. Additional semiconductor material is then epitaxially grown inside each trench between the elongated gates to form source-drain regions adjacent the channel regions formed by the elongated fins of the first semiconductor material located under the elongated gates.

Abstract: A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel. Sidewall spacers are formed on side walls of the elongated gates. Portions of the elongated fins located between the elongated gates are removed, along with the underlying insulation, to expose the underlying substrate. One or more semiconductor material layers are then epitaxially grown from the underlying substrate at locations between the elongated gates. The one or more semiconductor material layers may include an undoped epi-layer and an overlying doped epi-layer. The epitaxial material defines a source or drain of the transistor.

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: A method for uniformly planarizing a wafer that includes determining a first wafer warped value at a first zone on the wafer, determining a second wafer warped value at a second zone on the wafer, and calculating a pressure difference based on the first and second wafer warped values at the first and second zones is provided. The method also includes performing a chemical mechanical polishing of the wafer, applying a first pressure based on the first wafer warped value to the wafer at the first zone during the chemical mechanical polishing, and applying a second pressure based on the second wafer warped value to the wafer at the second zone during the chemical mechanical polishing, a difference between the first pressure and the second pressure based on the pressure difference.

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: A method for uniformly planarizing a wafer that includes determining a first wafer warped value at a first zone on the wafer, determining a second wafer warped value at a second zone on the wafer, and calculating a pressure difference based on the first and second wafer warped values at the first and second zones is provided. The method also includes performing a chemical mechanical polishing of the wafer, applying a first pressure based on the first wafer warped value to the wafer at the first zone during the chemical mechanical polishing, and applying a second pressure based on the second wafer warped value to the wafer at the second zone during the chemical mechanical polishing, a difference between the first pressure and the second pressure based on the pressure difference.

Abstract: An ellipsometer measures/monitors the change in polarization of light upon reflection from a wafer sample. The temperature of the wafer substrate surface and the film thickness are then simultaneously determined in situ using ellipsometry where the true wafer temperature is determined in real-time by the computer from a calculation based on the known temperature dependence of the refractive index of the wafer. The power output to the lamps is then adjusted accordingly to raise or lower the wafer temperature within the apparatus. This process continues automatically to maintain the desired temperature and film growth rate until the desired film thickness is achieved.