Abstract: The present invention relates to a method for etching a feature in an etch layer that has a thickness of more than 2 micrometers from an initial contact face for the etchant to an opposite bottom face of the etch layer, at a lateral feature position in the etch layer and with a critical lateral extension at the bottom face. The method includes fabricating, at the lateral feature position on the substrate layer, a mask feature from a mask-layer material, the mask feature having the critical lateral extension. The etch layer is deposited to a thickness of more than 2 micrometers, on the mask feature and on the substrate layer, from an etch-layer material, which is selectively etchable relative to the mask-layer material. Then, the feature is etched in the etch layer at the first lateral position with a lateral extension larger than the critical lateral extension, using an etchant that selectively removes the etch layer-material relative to the mask-layer material.

Abstract: Method for manufacturing a capacitor on a substrate, the capacitor including a first electrode (5) and a second electrode (12; 25), the first and second electrodes being separated by a cavity (16; 32), the substrate including an insulating surface layer (3), the first electrode (5) being arranged on the insulating surface layer a first metal body (7a; 20) being adjacent to the first electrode and arranged as anchor of the second electrode (12; 25) the second electrode being arranged as a beam-shaped body (12; 25) located on the first metal body and above the first electrode; the cavity (16; 32) being laterally demarcated by a sidewall of the first metal body.

Abstract: Method for manufacturing a capacitor on a substrate, the capacitor including a first electrode (5) and a second electrode (12; 25), the first and second electrodes being separated by a cavity (16; 32), the substrate including an insulating surface layer (3), the first electrode (5) being arranged on the insulating surface layer a first metal body (7a; 20) being adjacent to the first electrode and arranged as anchor of the second electrode (12; 25) the second electrode being arranged as a beam-shaped body (12; 25) located on the first metal body and above the first electrode; the cavity (16; 32) being laterally demarcated by a sidewall of the first metal body.

Abstract: The present invention relates to a method for etching a feature in an etch layer that has a thickness of more than 2 micrometers from an initial contact face for the etchant to an opposite bottom face of the etch layer, at a lateral feature position in the etch layer and with a critical lateral extension at the bottom face. The method includes fabricating, at the lateral feature position on the substrate layer, a mask feature from a mask-layer material, the mask feature having the critical lateral extension. The etch layer is deposited to a thickness of more than 2 micrometers, on the mask feature and on the substrate layer, from an etch-layer material, which is selectively etchable relative to the mask-layer material. Then, the feature is etched in the etch layer at the first lateral position with a lateral extension larger than the critical lateral extension, using an etchant that selectively removes the etch layer-material relative to the mask-layer material.

Abstract: A peak voltage protection circuit for protecting an associated High Voltage NPN transistor (T3) against breakdown, the protection circuit comprising a Low Voltage NPN element (T15) for sensing a sensor voltage related to a base-collector voltage of the associated High Voltage NPN transistor (T3). The circuit further comprises an activation circuit for limiting the base-collector voltage of the associated High Voltage NPN transistor (T3) upon triggering. The Low Voltage NPN element (15) is coupled to the activation circuit for triggering it upon the sensor voltage exceeding a breakdown voltage of the Low Voltage NPN transistor (T15).

Abstract: A detection circuit for detecting the output power of a power amplifier comprises a first current minor transistor (Ti 1) having a base, which is connectable to a power transistor (T10), and a collector, a RF detection means (RF-det) for detecting the RF current flowing through the current mirror transistor (T11). Said RF detection means (RFdet) is connected to the collector of said first current mirror transistor (T11). Said detection circuit further comprises a biasing means (bias-RF-det) for biasing said RF detection means (RF-det), wherein said biasing means is connected to said collector of said first current mirror (T11) and said RF detection means (RF-det).

Abstract: An RF power amplifier according to the invention comprises a plurality of parallel output transistors (HBT,1,1 to HBT,1,N) connected to a power supply. A plurality of base resistors (Rb,1,1 to Rb,1,N) for the output transistors (HBT,1,1 to HBT,1,N) and a plurality of input capacitors (Cb,1 to Cb,N), each coupled in parallel to receive an RF signal input and connected via at least one additional passive component to the inputs of each corresponding output transistor (HBT,1,1 to HBT,1,N), are provided An output for an RF output signal is obtained from the parallel connection of the output transistors (HBT,1,1 to HBT,1,N). The transistors (HBT,1,1 to HBT,1,N) are heterojunction bipolar transistors.

Abstract: A detection circuit for detecting the output power of a power amplifier comprises a first current minor transistor (Ti 1) having a base, which is connectable to a power transistor (T10), and a collector, a RF detection means (RF-det) for detecting the RF current flowing through the current mirror transistor (T11). Said RF detection means (RFdet) is connected to the collector of said first current mirror transistor (T11). Said detection circuit further comprises a biasing means (bias-RF-det) for biasing said RF detection means (RF-det), wherein said biasing means is connected to said collector of said first current mirror (T11) and said RF detection means (RF-det).

Abstract: An RF power amplifier according to the invention comprises a plurality of parallel output transistors (HBT,1,1 to HBT,1,N) connected to a power supply. A plurality of base resistors (Rb,1,1 to Rb,1,N) for the output transistors (HBT,1,1 to HBT,1,N) and a plurality of input capacitors (Cb,1 to Cb,N), each coupled in parallel to receive an RF signal input and connected via at least one additional passive component to the inputs of each corresponding output transistor (HBT,1,1 to HBT,1,N), are provided. An output for an RF output signal is obtained from the parallelconnection of the output transistors (HBT,1,1 to HBT,1,N). The transistors (HBT,1,1 to HBT,1,N) are heterojunction bipolar transistors.

Abstract: A semiconductor device comprising a silicon body (1) with a surface (2) which is adjoined by insulation regions of a first type (3) and insulation regions of a second type (4). The insulation regions of the first type (3) enclose active regions (5) which each comprise a bipolar transistor (6), the insulation regions of the second type (4) enclose active regions (7) which each comprise a MOS transistor (8). The insulation regions of the first type (3) are etched grooves (14) which are filled with insulating material (15) through deposition. The insulation regions of the second type (4) are silicon oxide regions obtained through local oxidation of the silicon body.

Abstract: A semiconductor device provided with a semiconductor substrate with a bipolar transistor having a collector region of a first conductivity type, a base region adjoining the collector region and of a second conductivity type opposed to the first, and an elongate emitter region of the first conductivity type adjoining the base region; the collector region, the base region, and the emitter region being provided with conductor tracks which are connected to conductive connection surfaces. The conductor track on the elongate emitter region of the semiconductor device has a connection to a connection surface for a further electrical connection at each of the two ends of the emitter region. The emitter region may be made longer in this manner because the length of the emitter region is effectively halved by the connections at the two ends. Consequently, charge carriers need be transported over no more than at most half the emitter length.

Abstract: A method of manufacturing a semiconductor device with a bipolar transistor (1) and a MOS transistor (2) formed in a silicon body (3) which for this purpose is provided with a field insulation region (4) by which semiconductor regions (6, 7) adjoining a surface (5) of said body are mutually insulated. A first region (6) is destined for the bipolar transistor and a second region (7) for the MOS transistor. The second region is provided with a gate dielectric (10). Then an electrode layer of non-crystalline silicon (11) is provided on the surface, which electrode layer is provided with a doping and in which electrode layer subsequently an emitter electrode (12) is formed on the first region and a gate electrode (13) on the second region.

Abstract: A method of manufacturing a semiconductor device with a bipolar transistor (1) and a MOS transistor (2) formed in a silicon body (3) which for this purpose is provided with a field insulation region (4) by which semiconductor regions (6, 7) adjoining a surface (5) of said body are mutually insulated. A first region (6) is to be used for the bipolar transistor and a second region for the MOS transistor. The two regions are provided in that order with a gate dielectric layer (10) and an auxiliary layer (11) of non-crystalline silicon. The auxiliary layer and the gate dielectric layer are subsequently removed from the first region. Then an electrode layer (13) of non-crystalline silicon is deposited. An emitter electrode (15) is formed in the electrode layer on the first region, and a gate electrode (16) is formed both in the electrode layer and in the auxiliary layer on the second region.

Abstract: A method of manufacturing a semiconductor device comprising a semiconductor body (1) with field insulation regions (14) formed by grooves (10; 24) filled with an insulating material (13) is disclosed. The grooves (10; 24) are etched into the semiconductor body (1) with the use of an etching mask (9) formed on an auxiliary layer (6) provided on a surface (5) of the semiconductor body (1). The auxiliary layer (6) is removed from the portion (11) of the surface (5) situated next to the etching mask (9) before the grooves (10; 24) are etched into the semiconductor body (1), and the auxiliary layer (6) is removed from the edge (12) of the surface (5) situated below the etching mask (9) after the grooves (10; 24) have been etched into the semiconductor body. Furthermore, a layer (13) of the insulating material is deposited on the semiconductor body (1), whereby the grooves (10; 24) are filled and the edge (12) of the surface (5) situated below the etching mask (9) is covered.

Abstract: A method of manufacturing a semiconductor device whereby on a surface (3) of a semiconductor body (1) a conductor track (21) of polycrystalline silicon insulated from the surface (3) is provided in a layer of doped polycrystalline silicon (11) provided on a layer of insulating material (10), and whereby a strip of polycrystalline silicon (19, 35) is formed between an edge (18) of the conductor (21) and a portion (24, 34) of the surface (3) adjoining the edge (18), after which a semiconductor zone (30) is formed through diffusion of dopant from the conductor (21) through the strip (19, 35) into the semiconductor body (1).