Abstract: A communication interface circuit for interfacing a processor with a plurty of application devices is provided. Circuitry monitors input/output (I/O) addresses passed on the processor's data transfer bus and provides a first enable signal when an I/O addresses indicates that operation of the communication interface circuit has been requested by the processor. Control logic, in response to the first enable signal, is then given access to configuration data passed on the data transfer bus associated with the one I/O address. The control logic interprets the data and produces a second enable signal in accordance therewith. A plurality of programmable controllers, in response to the second enable signal, are initialized by the configuration data. The interface circuit is then configured for a selected one of the application devices in terms of timing control, interrupt control and direct memory access control (DMA).