Abstract: A Phase Lock Loop (PLL) receives input signals from a local area network (LAN) and recovers data and clock signals therefrom. The PLL includes a charge pump which is responsive to pump-up or pump-down signals provided by a phase detector. A level determination circuitry scales the charge pump current in proportion to the time elapsing between transitions in the input signals. The charge pump, phase detector and level determination circuitry provide a constant average amps per radian gain and is insensitive to variations in the input signals.

Abstract: A high current CMOS circuit including a raised cosine signal generator for generating a raised cosine signal waveform and an input circuit arrangement for controlling the raised cosine signal generator is described. The raised cosine signal generator includes an output node to which a controlled chain of CMOS inverters are connected. The input circuit arrangement accepts an input signal, converts it into appropriate signals which drive respective inverters so that simultaneous conduction of inverter pairs is prevented. The off chip driver (OCD) minimizes ground bounce, electrical noise and radiation problems caused by large current transients or spikes (di/dt) that usually accompany such circuits.

Abstract: A circuit arrangement for recovering data from a communications network includes a phase lock loop (PLL) with a voltage controlled oscillator (VCO) and a circuit for automatically centering the VCO. The circuit arrangement includes a counter that stores a changeable digital word. The digital word provides an adjustable current for driving the VCO. Initially, the VCO is driven so that its output signal falls within a predetermined frequency range. An error voltage representing the difference between a predetermined voltage range is developed and is used to change the contents of the counter until the VCO is centered. Thereafter the count that causes centering of the VCO is locked in the counter and normal PLL function is enabled.