Abstract: A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.

Abstract: A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode.

Abstract: A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.

Abstract: A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode.

Abstract: A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.

Abstract: A technique for controlling a multiplicity of time-sorted queues with a single controller and supporting memory, which may be software-configured so as to allow the use of the controller in an implementation having a multiplicity and variety of output lines or channels. The technique includes receiving a plurality of packets from one or more packet flows at a respective time-based output port queue of the network switch, in which each packet has a timestamp associated therewith. Each output card memory can be divided into a plurality of queues, in which the number of queues corresponds to the number of flows received by the switch and the size of each queue is proportional to the fractional amount of the total bandwidth of the switch used by the corresponding packet flow.

Abstract: A technique for controlling a multiplicity of time-sorted queues with a single controller and supporting memory, which may be software-configured so as to allow the use of the controller in an implementation having a multiplicity and variety of output lines or channels. The technique includes receiving a plurality of packets from one or more packet flows at a respective time-based output port queue of the network switch, in which each packet has a timestamp associated therewith. Next, each packet is inserted into a respective timeslot of the output port queue, as indexed by its associated timestamp. The binary value of the timestamp is then partitioned into a plurality of sub-fields, each sub-field comprising one or more bits and corresponding to a predetermined level of acceleration bit-strings. Next, the values at respective locations in at least one memory configured to store a plurality of levels of acceleration bit-strings are asserted, as indexed by the respective sub-fields of bits.

Abstract: A computer system for transmitting packets includes a manager and scheduling elements for managing the transmission of the packets over one or more logical channels. The computer system can prioritize the transmission of packets based on the type of traffic and maintain quality of service (QoS) characteristics associated with a logical channel. In addition, the computer system can execute a threading process to ensure the efficient and timely transmission of certain types of packets without using any complex mathematical operations.