Abstract: A simulation technique that handles accesses to a frame of memory via a proxy object provides improved throughput in simulation environments. The proxy object, if present, processes the access at a head of a linked list of frames. If a check frame is not inserted in the list, the memory frame handles the request directly, but if a check frame is inserted, then the check operation is performed. The check frame can be a synchronization frame that blocks access to a memory frame while the check frame is present, or the check frame may be a breakpoint, watch or exception frame that calls a suitable handling routine. Additional check frames may be chained between the interface and the memory subsystem to handle synchronization, breakpoints, memory watches or other accesses to or information gathering associated with the memory frame.

Abstract: A simulation technique that handles accesses to a frame of memory via a proxy object provides improved throughput in simulation environments. The proxy object, if present, processes the access at a head of a linked list of frames. If a check frame is not inserted in the list, the memory frame handles the request directly, but if a check frame is inserted, then the check operation is performed. The check frame can be a synchronization frame that blocks access to a memory frame while the check frame is present, or the check frame may be a breakpoint, watch or exception frame that calls a suitable handling routine. Additional check frames may be chained between the interface and the memory subsystem to handle synchronization, breakpoints, memory watches or other accesses to or information gathering associated with the memory frame.

Abstract: A simulation technique that handles accesses to a frame of instruction memory by inserting a command object between a frame proxy and a memory frame provides improved throughput in simulation environments. The instruction frame, if present, processes the access to the frame. If an instruction frame is not present for the accessed frame, the memory frame handles the request directly. The instruction frame caches fetched and decoded instructions and may be inserted at the first access to a corresponding instruction memory frame. The instruction frame can track write accesses to instruction memory so that changes to the instruction memory can be reflected in the state of the instruction frame. Additional check frames may be chained between the interface and the memory frame to handle breakpoints, instruction memory watches or other access checks on the instruction memory frame.

Abstract: A simulation technique that handles accesses to a frame of memory via a proxy object provides improved throughput in simulation environments. The proxy object, if present, processes the access at a head of a linked list of frames. If a check frame is not inserted in the list, the memory frame handles the request directly, but if a check frame is inserted, then the check operation is performed. The check frame can be a synchronization frame that blocks access to a memory frame while the check frame is present, or the check frame may be a breakpoint, watch or exception frame that calls a suitable handling routine. Additional check frames may be chained between the interface and the memory subsystem to handle synchronization, breakpoints, memory watches or other accesses to or information gathering associated with the memory frame.

Abstract: A simulation technique that handles accesses to a frame of memory via a proxy object provides improved throughput in simulation environments. The proxy object, if present, processes the access at a head of a linked list of frames. If a check frame is not inserted in the list, the memory frame handles the request directly, but if a check frame is inserted, then the check operation is performed. The check frame can be a synchronization frame that blocks access to a memory frame while the check frame is present, or the check frame may be a breakpoint, watch or exception frame that calls a suitable handling routine. Additional check frames may be chained between the interface and the memory subsystem to handle synchronization, breakpoints, memory watches or other accesses to or information gathering associated with the memory frame.

Abstract: A simulation technique that handles accesses to a frame of memory via a proxy object provides improved throughput in simulation environments. The proxy object, if present, processes the access at a head of a linked list of frames. If a check frame is not inserted in the list, the memory frame handles the request directly, but if a check frame is inserted, then the check operation is performed. The check frame can be a synchronization frame that blocks access to a memory frame while the check frame is present, or the check frame may be a breakpoint, watch or exception frame that calls a suitable handling routine. Additional check frames may be chained between the interface and the memory subsystem to handle synchronization, breakpoints, memory watches or other accesses to or information gathering associated with the memory frame.

Abstract: A simulation technique that handles accesses to a frame of memory via a proxy object provides improved throughput in simulation environments. The proxy object, if present, processes the access at a head of a linked list of frames. If a check frame is not inserted in the list, the memory frame handles the request directly, but if a check frame is inserted, then the check operation is performed. The check frame can be a synchronization frame that blocks access to a memory frame while the check frame is present, or the check frame may be a breakpoint, watch or exception frame that calls a suitable handling routine. Additional check frames may be chained between the interface and the memory subsystem to handle synchronization, breakpoints, memory watches or other accesses to or information gathering associated with the memory frame.

Abstract: A simulation technique that handles accesses to a frame of instruction memory by inserting a command object between a frame proxy and a memory frame provides improved throughput in simulation environments. The instruction frame, if present, processes the access to the frame. If an instruction frame is not present for the accessed frame, the memory frame handles the request directly. The instruction frame caches fetched and decoded instructions and may be inserted at the first access to a corresponding instruction memory frame. The instruction frame can track write accesses to instruction memory so that changes to the instruction memory can be reflected in the state of the instruction frame. Additional check frames may be chained between the interface and the memory frame to handle breakpoints, instruction memory watches or other access checks on the instruction memory frame.

Abstract: A simulation technique that handles accesses to a frame of memory via a proxy object provides improved throughput in simulation environments. The proxy object, if present, processes the access at a head of a linked list of frames. If a check frame is not inserted in the list, the memory frame handles the request directly, but if a check frame is inserted, then the check operation is performed. The check frame can be a synchronization frame that blocks access to a memory frame while the check frame is present, or the check frame may be a breakpoint, watch or exception frame that calls a suitable handling routine. Additional check frames may be chained between the interface and the memory subsystem to handle synchronization, breakpoints, memory watches or other accesses to or information gathering associated with the memory frame.

Abstract: A simulation technique that handles accesses to a frame of instruction memory by inserting a command object between a frame proxy and a memory frame provides improved throughput in simulation environments. The instruction frame, if present, processes the access to the frame. If an instruction frame is not present for the accessed frame, the memory frame handles the request directly. The instruction frame caches fetched and decoded instructions and may be inserted at the first access to a corresponding instruction memory frame. The instruction frame can track write accesses to instruction memory so that changes to the instruction memory can be reflected in the state of the instruction frame. Additional check frames may be chained between the interface and the memory frame to handle breakpoints, instruction memory watches or other access checks on the instruction memory frame.

Abstract: A simulation technique that handles accesses to a frame of memory via a proxy object provides improved throughput in simulation environments. The proxy object, if present, processes the access at a head of a linked list of frames. If a check frame is not inserted in the list, the memory frame handles the request directly, but if a check frame is inserted, then the check operation is performed. The check frame can be a synchronization frame that blocks access to a memory frame while the check frame is present, or the check frame may be a breakpoint, watch or exception frame that calls a suitable handling routine. Additional check frames may be chained between the interface and the memory subsystem to handle synchronization, breakpoints, memory watches or other accesses to or information gathering associated with the memory frame.

Abstract: A simulation technique that handles accesses to a frame of instruction memory by inserting a command object between a frame proxy and a memory frame provides improved throughput in simulation environments. The instruction frame, if present, processes the access to the frame. If an instruction frame is not present for the accessed frame, the memory frame handles the request directly. The instruction frame caches fetched and decoded instructions and may be inserted at the first access to a corresponding instruction memory frame. The instruction frame can track write accesses to instruction memory so that changes to the instruction memory can be reflected in the state of the instruction frame. Additional check frames may be chained between the interface and the memory frame to handle breakpoints, instruction memory watches or other access checks on the instruction memory frame.

Abstract: A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. At least some of the processors in the system are organized into a hierarchy, and process an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive and an unconditional lock acquisition primitive, and an unconditional lock release primitive for releasing the lock from a particular processor. To prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. Furthermore, in order to ensure that the a processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized.

Abstract: A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. At least some of the processors in the system are organized into a hierarchy, and process an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive and an unconditional lock acquisition primitive, and an unconditional lock release primitive for releasing the lock from a particular processor. To prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. Furthermore, in order to ensure that the a processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized.

Abstract: A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. The method organizes at least some of the processors in the system into a hierarchy, and processes an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive and an unconditional lock acquisition primitive, and an unconditional lock release primitive for releasing the lock from a particular processor. In order to prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. Furthermore, in order to ensure that the a processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized.

Abstract: A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. The method organizes at least some of the processors in the system into a hierarchy, and processes an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive and an unconditional lock acquisition primitive, and an unconditional lock release primitive for releasing the lock from a particular processor. In order to prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. Furthermore, in order to ensure that the a processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized.