Abstract: A delta-sigma converter has coarse and fine ADCs, wherein an integrated error signal is coupled to the coarse ADC whose output drives a DAC to create feedback that achieves loop balance. The coarse ADC provides the most significant bits of the result. The integrated error signal is also applied to a fine ADC whose output bits are not incorporated into the feedback, but which are combined with those of the coarse ADC and the combination applied to a filter that averages the hunting that represents loop balance. A DC feed forward circuit shunts the integrator with a replica of the applied input signal to apply it to the coarse ADC through a summer, allowing its output to be just the integrated error signal without including the applied input. If continuous integration is used, an AC feed forward circuit provides a compensatory voltage that is removed from the integrator output (or alternatively, is added to its input) and that corrects for a frequency dependent error.

Abstract: A dual path analog-to-digital conversion method and system. The system includes a first and second circuits. The first and second circuits each convert an input analog signal into digital signals at differing sample rates. The circuit having the slower sampling rate aliases frequency components of the input analog signal that are higher than half that sampling rate. Frequency components causing the aliasing in the slower sampling circuit are replicated from the faster sampling circuit at the appropriate amplitude, folded into the aliased frequency, and subtracted from the output of the slower sampling circuit. The outputs of both sampling circuits are then merged. These techniques extend the bandwidth of the slower conversion system without degrading the low-frequency accuracy of the slower conversion system.

Abstract: A dual path analog-to-digital conversion method and system. The system includes a first and second circuits. The first and second circuits each convert an input analog signal into digital signals at differing sample rates. The circuit having the slower sampling rate aliases frequency components of the input analog signal that are higher than half that sampling rate. Frequency components causing the aliasing in the slower sampling circuit are replicated from the faster sampling circuit at the appropriate amplitude, folded into the aliased frequency, and subtracted from the output of the slower sampling circuit. The outputs of both sampling circuits are then merged. These techniques extend the bandwidth of the slower conversion system without degrading the low-frequency accuracy of the slower conversion system.

Abstract: An apparatus and method for signal processing in a root-mean-square (RMS) meter. In representative embodiments, the root-mean-square (RMS) meter includes an RMS converter having a converter input and a converter output. The RMS converter converts a time varying signal applied to the converter input to a signal at the converter output. The value of the signal at the converter output is indicative of the RMS value of the applied signal. The signal at the converter output comprises a non-time varying component and a time varying component as determined by a time constant of the RMS converter. The RMS meter further includes an inverting amplifier having an inverter input and an inverter output. The converter output is connected to the inverter input. In addition, the RMS meter includes a switch having first, second, and central contacts. The converter output is connected to the first contact, and the inverter output is connected to the second contact.

Abstract: An AC input signal is sampled with a plurality of sets of equally spaced samples, but whose sample interval between the samples does not exactly divide the period of the input signal. Nevertheless, and error cancellation technique allows ultra accurate measurements to be made. The samples in each set of the plurality of sets are supplied to a computational process that extracts some parameter; e.g., RMS voltage. The extracted parameter is in error, owing to the non aliquot nature of the sampling. The size of the error is related to, among other things, where on the input waveform the associated set began. The error is a period AC function of that starting location. By arranging for n-many sets to start at phase differences of 1/n apart on the input waveform, a series of n-many parameter.sub.i are obtained that are each of the form [result.sub.i +error.sub.i ]. Thus, the error.sub.i are sampled at aliquot locations along an error function, and therefore sum to zero. Thus, averaging the parameter.sub.

Abstract: An AC RMS voltmeter two RMS converters of the type where the RMS value of the output is proportional to the RMS value of the input. The input signal is coupled to a first RMS converter through an input coupling network that includes a DC block. The first RMS converter is of the analog variety having good high frequency response but with a short time constant. Its output is allowed to track the input at low input frequencies. The output of the first RMS converter is digitized by an analog-to-digital converter at a rate high enough to capture any significant ripple coming out of the first RMS converter and operated upon by a second RMS converter implemented digitally by a microprocessor. The sampling rate of the A/D converter need not be high enough to operate at the highest frequencies applied to the voltmeter, since these are converted to DC by the first RMS converter.

Abstract: A track/hold circuit having a holding capacitor whose voltage is replicated by a non-inverting unity gain output amplifier combines both high-speed operation and compensation for errors affecting linearity. The holding capacitor is coupled to the input voltage through two junction field effect transistors (JFET's) that are in series. Both JFET's are on when the circuit is in TRACK. To switch from TRACK to HOLD the JFET nearest the holding capacitor is switched off before the JFET nearest the input voltage. A first source of pedestal error in the output voltage from the output amplifier is rendered constant and well behaved, so that it may be calibrated out. This rendering is accomplished by limiting the voltage swing on the gate of the JFET nearest the holding capacitor to be between the input voltage itself (when that JFET is on) at one extreme and a fixed voltage offset from the input voltage (when that JFET is off) at the other extreme.

Abstract: A method of calibration for a voltage to time converter in order to increment delays by a fraction of a clock cycle known as an interpolator period is disclosed. The method of calibration compares differences in measurements of a constant and repetitive input waveform while changing current, base voltage threshold, incremental voltage threshold, or any combination thereof to minimize the calibration error for a predetermined number of interpolator periods designed to equal an integral number of clock cycles.

Abstract: An ac measuring instrument automatically compensates an input attenuator to achieve precision frequency response. The output of the input attenuator is applied to both the conventional measurement portion of the instrument and to an amplifier of variable gain. The output of the variable gain amplifier drives either a resistive or capacitive impedance coupled to the output of the input attenuator. The impedance is thus driven by a voltage that is a scaled replica of the output of the input attenuator. That scale factor may vary from near zero to greater than one, and the impedance acts as a virtual trimmer whose apparent value varies as the scale factor of its actual value according to the gain established for the variable gain amplifier. The proper gain therefor is determined by a servo loop that applies a test pulse to the input attenuator and subsequently samples the output thereof at least twice.